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@article{DBLP:journals/sigarch/AziziMPH09,
  author       = {Omid Azizi and
                  Aqeel Mahesri and
                  Sanjay J. Patel and
                  Mark Horowitz},
  title        = {Area-efficiency in {CMP} core design: co-optimization of microarchitecture
                  and physical design},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {2},
  pages        = {56--65},
  year         = {2009},
  url          = {https://doi.org/10.1145/1577129.1577138},
  doi          = {10.1145/1577129.1577138},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/AziziMPH09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/ChenAD09,
  author       = {Jianwei Chen and
                  Murali Annavaram and
                  Michel Dubois},
  title        = {SlackSim: a platform for parallel simulations of CMPs on CMPs},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {2},
  pages        = {20--29},
  year         = {2009},
  url          = {https://doi.org/10.1145/1577129.1577134},
  doi          = {10.1145/1577129.1577134},
  timestamp    = {Tue, 07 Dec 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/sigarch/ChenAD09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/JesshopeLZ09,
  author       = {Chris R. Jesshope and
                  Mike Lankamp and
                  Li Zhang},
  title        = {The implementation of an {SVP} many-core processor and the evaluation
                  of its memory architecture},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {2},
  pages        = {38--45},
  year         = {2009},
  url          = {https://doi.org/10.1145/1577129.1577136},
  doi          = {10.1145/1577129.1577136},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/JesshopeLZ09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/JouppiKT09,
  author       = {Norman P. Jouppi and
                  Rakesh Kumar and
                  Dean M. Tullsen},
  title        = {Introduction to the special issue on the 2008 workshop on design,
                  analysis, and simulation of chip multiprocessors (dasCMP'08)},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {2},
  pages        = {1},
  year         = {2009},
  url          = {https://doi.org/10.1145/1577129.1577131},
  doi          = {10.1145/1577129.1577131},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/JouppiKT09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/MonchieroAFOF09,
  author       = {Matteo Monchiero and
                  Jung Ho Ahn and
                  Ayose Falc{\'{o}}n and
                  Daniel Ortega and
                  Paolo Faraboschi},
  title        = {How to simulate 1000 cores},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {2},
  pages        = {10--19},
  year         = {2009},
  url          = {https://doi.org/10.1145/1577129.1577133},
  doi          = {10.1145/1577129.1577133},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/MonchieroAFOF09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Musoll09,
  author       = {Enric Musoll},
  title        = {Mesh-based many-core performance under process variations: a core
                  yield perspective},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {4},
  pages        = {27--34},
  year         = {2009},
  url          = {https://doi.org/10.1145/1730963.1730966},
  doi          = {10.1145/1730963.1730966},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Musoll09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Musoll09a,
  author       = {Enric Musoll},
  title        = {Leakage-saving opportunities in mesh-based massive multi-core architectures},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {5},
  pages        = {1--7},
  year         = {2009},
  url          = {https://doi.org/10.1145/1755235.1755237},
  doi          = {10.1145/1755235.1755237},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Musoll09a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/NaeemCLJ09,
  author       = {Abdul Naeem and
                  Xiaowen Chen and
                  Zhonghai Lu and
                  Axel Jantsch},
  title        = {Scalability of relaxed consistency models in NoC based multicore architectures},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {5},
  pages        = {8--15},
  year         = {2009},
  url          = {https://doi.org/10.1145/1755235.1755238},
  doi          = {10.1145/1755235.1755238},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/NaeemCLJ09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Nikolov09,
  author       = {Angel V. Nikolov},
  title        = {Queuing theoretic model for a multiprocessor with private caches and
                  shared memory},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {4},
  pages        = {35--44},
  year         = {2009},
  url          = {https://doi.org/10.1145/1730963.1730967},
  doi          = {10.1145/1730963.1730967},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Nikolov09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/PurnaprajnaPR09,
  author       = {Madhura Purnaprajna and
                  Mario Porrmann and
                  Ulrich R{\"{u}}ckert},
  title        = {Run-time reconfigurability in embedded multiprocessors},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {2},
  pages        = {30--37},
  year         = {2009},
  url          = {https://doi.org/10.1145/1577129.1577135},
  doi          = {10.1145/1577129.1577135},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/PurnaprajnaPR09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/SharmaKB09,
  author       = {Sandeep Sharma and
                  Karanjeet Singh Kahlon and
                  P. K. Bansal},
  title        = {Reliability and path length analysis of irregular fault tolerant multistage
                  interconnection network},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {5},
  pages        = {16--23},
  year         = {2009},
  url          = {https://doi.org/10.1145/1755235.1755239},
  doi          = {10.1145/1755235.1755239},
  timestamp    = {Thu, 15 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/SharmaKB09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/SinghBM09,
  author       = {Karan Singh and
                  Major Bhadauria and
                  Sally A. McKee},
  title        = {Real time power estimation and thread scheduling via performance counters},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {2},
  pages        = {46--55},
  year         = {2009},
  url          = {https://doi.org/10.1145/1577129.1577137},
  doi          = {10.1145/1577129.1577137},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/SinghBM09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Thomasian09,
  author       = {Alexander Thomasian},
  title        = {Publications on storage and systems research},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {4},
  pages        = {1--26},
  year         = {2009},
  url          = {https://doi.org/10.1145/1730963.1730965},
  doi          = {10.1145/1730963.1730965},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Thomasian09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Thorson09,
  author       = {Mark Thorson},
  title        = {Internet nuggets},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {2},
  pages        = {66--69},
  year         = {2009},
  url          = {https://doi.org/10.1145/1577129.1577140},
  doi          = {10.1145/1577129.1577140},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Thorson09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Thorson09a,
  author       = {Mark Thorson},
  title        = {Internet nuggets},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {4},
  pages        = {45--51},
  year         = {2009},
  url          = {https://doi.org/10.1145/1730963.1730969},
  doi          = {10.1145/1730963.1730969},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Thorson09a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/Thorson09b,
  author       = {Mark Thorson},
  title        = {Internet nuggets},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {5},
  pages        = {24--30},
  year         = {2009},
  url          = {https://doi.org/10.1145/1755235.1755241},
  doi          = {10.1145/1755235.1755241},
  timestamp    = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/Thorson09b.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/sigarch/ZengYGP09,
  author       = {Hui Zeng and
                  Matt T. Yourst and
                  Kanad Ghose and
                  Dmitry Ponomarev},
  title        = {MPTLsim: a cycle-accurate, full-system simulator for x86-64 multicore
                  architectures with coherent caches},
  journal      = {{SIGARCH} Comput. Archit. News},
  volume       = {37},
  number       = {2},
  pages        = {2--9},
  year         = {2009},
  url          = {https://doi.org/10.1145/1577129.1577132},
  doi          = {10.1145/1577129.1577132},
  timestamp    = {Thu, 25 Aug 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/sigarch/ZengYGP09.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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