Search dblp for Publications

export results for "toc:db/journals/ipsj/ipsj7.bht:"

 download as .bib file

@article{DBLP:journals/ipsj/AkasakaAYT14,
  author       = {Hiroyuki Akasaka and
                  Shin{-}ya Abe and
                  Masao Yanagisawa and
                  Nozomu Togawa},
  title        = {Energy-efficient High-level Synthesis for {HDR} Architecture with
                  Multi-stage Clock Gating},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {74--80},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.74},
  doi          = {10.2197/IPSJTSLDM.7.74},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ipsj/AkasakaAYT14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/ChakrabartyADNWY14,
  author       = {Krishnendu Chakrabarty and
                  Mukesh Agrawal and
                  Sergej Deutsch and
                  Brandon Noia and
                  Ran Wang and
                  Fangming Ye},
  title        = {Test and Design-for-Testability Solutions for 3D Integrated Circuits},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {56--73},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.56},
  doi          = {10.2197/IPSJTSLDM.7.56},
  timestamp    = {Thu, 09 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ipsj/ChakrabartyADNWY14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/HagioYT14,
  author       = {Yuta Hagio and
                  Masao Yanagisawa and
                  Nozomu Togawa},
  title        = {A Delay-variation-aware High-level Synthesis Algorithm for {RDR} Architectures},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {81--90},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.81},
  doi          = {10.2197/IPSJTSLDM.7.81},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ipsj/HagioYT14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/Hara-AzumiMTHT14,
  author       = {Yuko Hara{-}Azumi and
                  Toshinobu Matsuba and
                  Hiroyuki Tomiyama and
                  Shinya Honda and
                  Hiroaki Takada},
  title        = {Impact of Resource Sharing and Register Retiming on Area and Performance
                  of FPGA-based Designs},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {37--45},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.37},
  doi          = {10.2197/IPSJTSLDM.7.37},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/Hara-AzumiMTHT14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/Ho14,
  author       = {Tsung{-}Yi Ho},
  title        = {Design Automation for Digital Microfluidic Biochips},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {16--26},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.16},
  doi          = {10.2197/IPSJTSLDM.7.16},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/Ho14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/JiangZW14,
  author       = {Xin Jiang and
                  Lian Zeng and
                  Takahiro Watanabe},
  title        = {A Sophisticated Routing Algorithm in 3D NoC with Fixed TSVs for Low
                  Energy and Latency},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {101--109},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.101},
  doi          = {10.2197/IPSJTSLDM.7.101},
  timestamp    = {Tue, 26 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/JiangZW14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/JoMF14,
  author       = {Satoshi Jo and
                  Takeshi Matsumoto and
                  Masahiro Fujita},
  title        = {SAT-based Automatic Rectification and Debugging of Combinational Circuits
                  with {LUT} Insertions},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {46--55},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.46},
  doi          = {10.2197/IPSJTSLDM.7.46},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/JoMF14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/KusakabeS14,
  author       = {Shingo Kusakabe and
                  Kenshu Seto},
  title        = {Forwarding Unit Generation for Loop Pipelining in High-level Synthesis},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {119--124},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.119},
  doi          = {10.2197/IPSJTSLDM.7.119},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/KusakabeS14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/NagaiHI14,
  author       = {Eriko Nagai and
                  Atsushi Hashimoto and
                  Nagisa Ishiura},
  title        = {Reinforcing Random Testing of Arithmetic Optimization of {C} Compilers
                  by Scaling up Size and Number of Expressions},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {91--100},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.91},
  doi          = {10.2197/IPSJTSLDM.7.91},
  timestamp    = {Sun, 22 Oct 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/NagaiHI14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/Tomiyama14,
  author       = {Hiroyuki Tomiyama},
  title        = {Message from the Editor-in-Chief},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {1},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.1},
  doi          = {10.2197/IPSJTSLDM.7.1},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/Tomiyama14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/WakabaWNI14,
  author       = {Yoichi Wakaba and
                  Shin'ichi Wakabayashi and
                  Shinobu Nagayama and
                  Masato Inagi},
  title        = {An Area Efficient Regular Expression Matching Engine Using Partial
                  Reconfiguration for Quick Pattern Updating},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {110--118},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.110},
  doi          = {10.2197/IPSJTSLDM.7.110},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/WakabaWNI14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/ZhangMKA14,
  author       = {Hao Zhang and
                  Hiroki Matsutani and
                  Michihiro Koibuchi and
                  Hideharu Amano},
  title        = {Dynamic Power Consumption Optimization for Inductive-Coupling based
                  Wireless 3D NoCs},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {27--36},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.27},
  doi          = {10.2197/IPSJTSLDM.7.27},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/ZhangMKA14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ipsj/ZhuangS14,
  author       = {Jingcheng Zhuang and
                  Robert Bogdan Staszewski},
  title        = {All-Digital {RF} Phase-Locked Loops Exploiting Phase Prediction},
  journal      = {{IPSJ} Trans. Syst. {LSI} Des. Methodol.},
  volume       = {7},
  pages        = {2--15},
  year         = {2014},
  url          = {https://doi.org/10.2197/ipsjtsldm.7.2},
  doi          = {10.2197/IPSJTSLDM.7.2},
  timestamp    = {Tue, 29 Sep 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ipsj/ZhuangS14.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.