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@inproceedings{DBLP:conf/isvlsi/AlsharqawiE05,
author = {Abdelhalim Alsharqawi and
Abdel Ejnioui},
title = {Synthesis of Self-Resetting Stage Logic Pipelines},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {260--262},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.70},
doi = {10.1109/ISVLSI.2005.70},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/AlsharqawiE05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/AtluriK05,
author = {Indrajit Atluri and
Ashwin K. Kumaraswamy},
title = {Energy Efficient Architectures for the Log-MAP Decoder through Intelligent
Memory Usage},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {263--265},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.29},
doi = {10.1109/ISVLSI.2005.29},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/AtluriK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/Breuer05,
author = {Melvin A. Breuer},
title = {Let's Think Analog},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {2--5},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.48},
doi = {10.1109/ISVLSI.2005.48},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/Breuer05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/CadenasMJ05,
author = {Oswaldo Cadenas and
Graham M. Megson and
Daniel Jones},
title = {A New Organization for a Perceptron-Based Branch Predictor and Its
{FPGA} Implementation},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {305--306},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.11},
doi = {10.1109/ISVLSI.2005.11},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/CadenasMJ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ChenCOK05,
author = {Guilin Chen and
Guangyu Chen and
Ozcan Ozturk and
Mahmut T. Kandemir},
title = {Exploiting Inter-Processor Data Sharing for Improving Behavior of
Multi-Processor SoCs},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {90--95},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.32},
doi = {10.1109/ISVLSI.2005.32},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ChenCOK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ChouliarasJKN05,
author = {Vassilios A. Chouliaras and
Tom R. Jacobs and
Ashwin K. Kumaraswamy and
Jos{\'{e}} L. N{\'{u}}{\~{n}}ez{-}Y{\'{a}}{\~{n}}ez},
title = {Configurable Multiprocessors for High-Performance {MPEG-4} Video Coding},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {272--273},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.24},
doi = {10.1109/ISVLSI.2005.24},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ChouliarasJKN05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ChuehPZ05,
author = {Juang{-}Ying Chueh and
Marios C. Papaefthymiou and
Conrad H. Ziesler},
title = {Two-Phase Resonant Clock Distribution},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {65--70},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.74},
doi = {10.1109/ISVLSI.2005.74},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ChuehPZ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/DickK05,
author = {Joshua R. Dick and
Kenneth B. Kent},
title = {Analysis of Incremental Communication for Multilayer Neural Networks
on a Field Programmable Gate Array},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {252--254},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.18},
doi = {10.1109/ISVLSI.2005.18},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/DickK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/DuttaRT05,
author = {Avijit Dutta and
Terence Rodrigues and
Nur A. Touba},
title = {Low Cost Test Vector Compression/Decompression Scheme for Circuits
with a Reconfigurable Serial Multiplier},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {200--205},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.49},
doi = {10.1109/ISVLSI.2005.49},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/DuttaRT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/EbendtD05,
author = {R{\"{u}}diger Ebendt and
Rolf Drechsler},
title = {Quasi-Exact {BDD} Minimization Using Relaxed Best-First Search},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {59--64},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.59},
doi = {10.1109/ISVLSI.2005.59},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/EbendtD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/GalCHM05,
author = {Bertrand Le Gal and
Emmanuel Casseau and
Sylvain Huet and
Eric Martin},
title = {Pipelined Memory Controllers for {DSP} Applications Handling Unpredictable
Data Accesses},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {268--269},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.56},
doi = {10.1109/ISVLSI.2005.56},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/GalCHM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/GhoshVB05,
author = {Soumik Ghosh and
Soujanya Venigalla and
Magdy A. Bayoumi},
title = {Design and Implementaion of a 2D-DCT Architecture Using Coefficient
Distributed Arithmetic},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {162--166},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.25},
doi = {10.1109/ISVLSI.2005.25},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/GhoshVB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/GopalanGK05,
author = {Ranganath Gopalan and
Chandramouli Gopalakrishnan and
Srinivas Katkoori},
title = {Leakage Power Driven Behavioral Synthesis of Pipelined Datapaths},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {167--172},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.46},
doi = {10.1109/ISVLSI.2005.46},
timestamp = {Sun, 12 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/GopalanGK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/GuoP05,
author = {Hui Guo and
Sri Parameswaran},
title = {Balancing System Level Pipelines with Stage Voltage Scaling},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {287--289},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.20},
doi = {10.1109/ISVLSI.2005.20},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/GuoP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/GuoS05,
author = {Xinyu Guo and
Carl Sechen},
title = {High Speed Redundant Adder and Divider in Output Prediction Logic},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {34--41},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.38},
doi = {10.1109/ISVLSI.2005.38},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/GuoS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/GuoYCEKM05,
author = {Jong{-}Ru Guo and
Chao You and
Michael Chu and
Okan Erdogan and
Russell P. Kraft and
John F. McDonald},
title = {A High Speed Reconfigurable Gate Array for Gigahertz Applications},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {124--129},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.8},
doi = {10.1109/ISVLSI.2005.8},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/GuoYCEKM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/HanEA05,
author = {Jong Hun Han and
Ahmet T. Erdogan and
Tughrul Arslan},
title = {High Speed Max-Log-MAP Turbo {SISO} Decoder Implementation Using Branch
Metric Normalization},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {173--178},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.37},
doi = {10.1109/ISVLSI.2005.37},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/HanEA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/HariyamaCOK05,
author = {Masanori Hariyama and
Weisheng Chong and
Sho Ogata and
Michitaka Kameyama},
title = {Novel Switch Block Architecture Using Non-Volatile Functional Pass-Gate
for Multi-Context FPGAs},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {46--50},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.52},
doi = {10.1109/ISVLSI.2005.52},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/HariyamaCOK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/HeSCYTGS05,
author = {Fei He and
Xiaoyu Song and
Lerong Cheng and
Guowu Yang and
Zhiwei Tang and
Ming Gu and
Jia{-}Guang Sun},
title = {A Hierachical Method for Wiring and Congestion Prediction},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {307--308},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.6},
doi = {10.1109/ISVLSI.2005.6},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/HeSCYTGS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/HostetlerX05,
author = {Daniel Hostetler and
Yuan Xie},
title = {Adaptive Power Management in Software Radios Using Resolution Adaptive
Analog to Digital Converters},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {186--191},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.14},
doi = {10.1109/ISVLSI.2005.14},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/HostetlerX05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/HuangV05,
author = {Renqiu Huang and
Ranga Vemuri},
title = {Sensitivity Analysis of a Cluster-Based Interconnect Model for FPGAs},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {250--251},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.68},
doi = {10.1109/ISVLSI.2005.68},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/HuangV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/JangXB05,
author = {Jinwook Jang and
Sheng Xu and
Wayne P. Burleson},
title = {Jitter in Deep Sub-Micron Interconnect},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {84--89},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.45},
doi = {10.1109/ISVLSI.2005.45},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/JangXB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/KyogokuINUOM05,
author = {Takanori Kyogoku and
Junpei Inoue and
Hidenari Nakashima and
Takumi Uezono and
Kenichi Okada and
Kazuya Masu},
title = {Wire Length Distribution Model Considering Core Utilization for System
on Chip},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {276--277},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.76},
doi = {10.1109/ISVLSI.2005.76},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/KyogokuINUOM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LeeJA05,
author = {Il{-}soo Lee and
Jae{-}Hoon Jeong and
Anthony P. Ambler},
title = {Using the Nonlinear Property of {FSR} and Dictionary Coding for Reduction
of Test Volume},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {194--199},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.75},
doi = {10.1109/ISVLSI.2005.75},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LeeJA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LeeLA05,
author = {Il{-}soo Lee and
Yu{-}Ting Lin and
Anthony P. Ambler},
title = {Reduction of Power and Test Time by Removing Cluster of Don't-Care
from Test Data Set},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {255--256},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.63},
doi = {10.1109/ISVLSI.2005.63},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LeeLA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LeeVI05,
author = {Jooheung Lee and
Narayanan Vijaykrishnan and
Mary Jane Irwin},
title = {High Performance Array Processor for Video Decoding},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {28--33},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.36},
doi = {10.1109/ISVLSI.2005.36},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LeeVI05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiFTM05,
author = {Lun Li and
Alex Fit{-}Florea and
Mitchell A. Thornton and
David W. Matula},
title = {Hardware Implementation of an Additive Bit-Serial Algorithm for the
Discrete Logarithm Modulo 2\({}^{\mbox{k}}\)},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {130--135},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.35},
doi = {10.1109/ISVLSI.2005.35},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LiFTM05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiK05,
author = {Feihui Li and
Mahmut T. Kandemir},
title = {Increasing Data {TLB} Resilience to Transient Errors},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {297--298},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.43},
doi = {10.1109/ISVLSI.2005.43},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LiK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiRP05,
author = {Wei Li and
Sudhakar M. Reddy and
Irith Pomeranz},
title = {On Reducing Peak Current and Power during Test},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {156--161},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.53},
doi = {10.1109/ISVLSI.2005.53},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LiRP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LiuF05,
author = {Yijun Liu and
Stephen B. Furber},
title = {A Low Power Embedded Dataflow Coprocessor},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {246--247},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.9},
doi = {10.1109/ISVLSI.2005.9},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LiuF05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/LivingstonNZTA05,
author = {Adam R. Livingston and
Hau T. Ngo and
Ming Z. Zhang and
Li Tao and
Vijayan K. Asari},
title = {Design of a Real Time System for Nonlinear Enhancement of Video Streams
by an Integrated Neighborhood Dependent Approach},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {301--302},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.28},
doi = {10.1109/ISVLSI.2005.28},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/LivingstonNZTA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MahalingamR05,
author = {Venkataraman Mahalingam and
N. Ranganathan},
title = {A Nonlinear Programming Based Power Optimization Methodology for Gate
Sizing and Voltage Selection},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {180--185},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.12},
doi = {10.1109/ISVLSI.2005.12},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/MahalingamR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MailiSWQD05,
author = {Alexander Maili and
Christian Steger and
Reinhold Weiss and
Rob Quigley and
Damian Dalton},
title = {Reducing the Communication Bottleneck via On-Chip Cosimulation of
Gate-Level {HDL} and C-Models on a Hardware Accelerator},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {290--291},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.61},
doi = {10.1109/ISVLSI.2005.61},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/MailiSWQD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MiyanoWK05,
author = {Mototsugu Miyano and
Minoru Watanabe and
Fuminori Kobayashi},
title = {Optically Differential Reconfigurable Gate Array Using an Optical
System with VCSELs},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {274--275},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.54},
doi = {10.1109/ISVLSI.2005.54},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/MiyanoWK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/MohantyVML05,
author = {Saraju P. Mohanty and
Ramakrishna Velagapudi and
Valmiki Mukherjee and
Hao Li},
title = {Reduction of Direct Tunneling Power Dissipation during Behavioral
Synthesis of Nanometer {CMOS} Circuits},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {248--249},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.62},
doi = {10.1109/ISVLSI.2005.62},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/MohantyVML05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/NatarajanSMB05,
author = {Aiyappan Natarajan and
Vijay Shankar and
Atul Maheshwari and
Wayne P. Burleson},
title = {Sensing Design Issues in Deep Submicron {CMOS} SRAMs},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {42--45},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.67},
doi = {10.1109/ISVLSI.2005.67},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/NatarajanSMB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/NgoGA05,
author = {Hau T. Ngo and
Rajkiran Gottumukkal and
Vijayan K. Asari},
title = {A Flexible and Efficient Hardware Architecture for Real-Time Face
Recognition Based on Eigenface},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {280--281},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.5},
doi = {10.1109/ISVLSI.2005.5},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/NgoGA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/NiemannPR05,
author = {J{\"{o}}rg{-}Christian Niemann and
Mario Porrmann and
Ulrich R{\"{u}}ckert},
title = {A Scalable Parallel SoC Architecture for Network Processors},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {311--313},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.13},
doi = {10.1109/ISVLSI.2005.13},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/NiemannPR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/OttaviSLPC05,
author = {Marco Ottavi and
Luca Schiano and
Fabrizio Lombardi and
Salvatore Pontarelli and
Gian Carlo Cardarilli},
title = {Evaluating the Data Integrity of Memory Systems by Configurable Markov
Models},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {257--259},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.30},
doi = {10.1109/ISVLSI.2005.30},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/OttaviSLPC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/OttaviVLPS05,
author = {Marco Ottavi and
Vamsi Vankamamidi and
Fabrizio Lombardi and
Salvatore Pontarelli and
Adelio Salsano},
title = {Design of a {QCA} Memory with Parallel Read/Serial Write},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {292--294},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.27},
doi = {10.1109/ISVLSI.2005.27},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/OttaviVLPS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/PengL05,
author = {Yuantao Peng and
Xun Liu},
title = {{RITC:} Repeater Insertion with Timing Target Compensation},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {299--300},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.65},
doi = {10.1109/ISVLSI.2005.65},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/PengL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/PomeranzVR05,
author = {Irith Pomeranz and
Srikanth Venkataraman and
Sudhakar M. Reddy},
title = {Fault Diagnosis and Fault Model Aliasing},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {206--211},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.34},
doi = {10.1109/ISVLSI.2005.34},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/PomeranzVR05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/RachlinSG05,
author = {Eric Rachlin and
John E. Savage and
Benjamin Gojman},
title = {Analysis of a Mask-Based Nanowire Decoder},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {6--13},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.17},
doi = {10.1109/ISVLSI.2005.17},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/RachlinSG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/RamamurthiMOC05,
author = {Vijaykumar Ramamurthi and
Jason McCollum and
Christopher Ostler and
Karam S. Chatha},
title = {System Level Methodology for Programming {CMP} Based Multi-Threaded
Network Processor Architectures},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {110--116},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.71},
doi = {10.1109/ISVLSI.2005.71},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/RamamurthiMOC05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/RaoHTD05,
author = {A. Rao and
Th. Haniotakis and
Y. Tsiatouhas and
H. Djemil},
title = {The Use of Pre-Evaluation Phase in Dynamic {CMOS} Logic},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {270--271},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.72},
doi = {10.1109/ISVLSI.2005.72},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/RaoHTD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/RautelaK05,
author = {Deepak Rautela and
Rajendra S. Katti},
title = {Design and Implementation of {FPGA} Router for Efficient Utilization
of Heterogeneous Routing Resources},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {232--237},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.26},
doi = {10.1109/ISVLSI.2005.26},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/RautelaK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/RusuIT05,
author = {Ana Rusu and
Mohammed Ismail and
Hannu Tenhunen},
title = {A Modified Cascaded Sigma-Delta Modulator with Improved Linearity},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {77--82},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.10},
doi = {10.1109/ISVLSI.2005.10},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/RusuIT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SaputraOVKB05,
author = {Hendra Saputra and
Ozcan Ozturk and
Narayanan Vijaykrishnan and
Mahmut T. Kandemir and
Richard R. Brooks},
title = {A Data-Driven Approach for Embedded Security},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {104--109},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.4},
doi = {10.1109/ISVLSI.2005.4},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SaputraOVKB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SathePZ05,
author = {Visvesh S. Sathe and
Marios C. Papaefthymiou and
Conrad H. Ziesler},
title = {Boost Logic: {A} High Speed Energy Recovery Circuit Family},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {22--27},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.22},
doi = {10.1109/ISVLSI.2005.22},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SathePZ05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SchubertB05,
author = {Tobias Schubert and
Bernd Becker},
title = {Lemma Exchange in a Microcontroller Based Parallel {SAT} Solver},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {142--147},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.47},
doi = {10.1109/ISVLSI.2005.47},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SchubertB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ShaoGYW05,
author = {Muzhou Shao and
Youxin Gao and
Li{-}Pen Yuan and
Martin D. F. Wong},
title = {{IR} Drop and Ground Bounce Awareness Timing Model},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {226--231},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.44},
doi = {10.1109/ISVLSI.2005.44},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ShaoGYW05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ShiFDGHS05,
author = {Junhao Shi and
G{\"{o}}rschwin Fey and
Rolf Drechsler and
Andreas Glowatz and
Friedrich Hapke and
J{\"{u}}rgen Schl{\"{o}}ffel},
title = {{PASSAT:} Efficient SAT-Based Test Pattern Generation for Industrial
Circuits},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {212--217},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.55},
doi = {10.1109/ISVLSI.2005.55},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ShiFDGHS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SmailagicSMRT05,
author = {Asim Smailagic and
Daniel P. Siewiorek and
Uwe Maurer and
Anthony Rowe and
Karen P. Tang},
title = {eWatch: Context Sensitive System Design Case Study},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {98--103},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.31},
doi = {10.1109/ISVLSI.2005.31},
timestamp = {Mon, 22 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/SmailagicSMRT05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/SunHGCMS05,
author = {Sheng Sun and
Yi Han and
Xinyu Guo and
Kian Haur Chong and
Larry McMurchie and
Carl Sechen},
title = {409ps 4.7 {FO4} 64b Adder Based on Output Prediction Logic in 0.18um
{CMOS}},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {52--58},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.2},
doi = {10.1109/ISVLSI.2005.2},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/SunHGCMS05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/TatapudiD05,
author = {Suryanarayana Tatapudi and
Jos{\'{e}} G. Delgado{-}Frias},
title = {A High Performance Hybrid Wave-Pipelined Multiplier},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {282--283},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.7},
doi = {10.1109/ISVLSI.2005.7},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/TatapudiD05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ThomasB05,
author = {Alexander Thomas and
J{\"{u}}rgen Becker},
title = {Multi-Grained Reconfigurable Datapath Structures for Online-Adaptive
Reconfigurable Hardware Architectures},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {118--123},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.51},
doi = {10.1109/ISVLSI.2005.51},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ThomasB05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ThondapuES05,
author = {Charan Thondapu and
Praveen Elakkumanan and
Ramalingam Sridhar},
title = {{RG-SRAM:} {A} Low Gate Leakage Memory Design},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {295--296},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.64},
doi = {10.1109/ISVLSI.2005.64},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ThondapuES05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/VasudevanLP05,
author = {Dilip P. Vasudevan and
Parag K. Lala and
James Patrick Parkerson},
title = {{CMOS} Realization of Online Testable Reversible Logic Gates},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {309--310},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.23},
doi = {10.1109/ISVLSI.2005.23},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/VasudevanLP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WatanabeK05,
author = {Minoru Watanabe and
Fuminori Kobayashi},
title = {An Improved Dynamic Optically Reconfigurable Gate Array},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {136--141},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.16},
doi = {10.1109/ISVLSI.2005.16},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/WatanabeK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WestraG05,
author = {Jurjen Westra and
Patrick Groeneveld},
title = {Post-Placement Pin Optimiztion},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {238--243},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.57},
doi = {10.1109/ISVLSI.2005.57},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/WestraG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WestraG05a,
author = {Jurjen Westra and
Patrick Groeneveld},
title = {Towards Integration of Quadratic Placement and Pin Assignment},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {284--286},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.73},
doi = {10.1109/ISVLSI.2005.73},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/WestraG05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/WuL05,
author = {Meng{-}Chiou Wu and
Rung{-}Bin Lin},
title = {A Comparative Study on Dicing of Multiple Project Wafers},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {314--315},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.3},
doi = {10.1109/ISVLSI.2005.3},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/WuL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/X05,
title = {Message from the Technical Program Chair},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.50},
doi = {10.1109/ISVLSI.2005.50},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/X05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/X05a,
title = {Symposium Committees},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.69},
doi = {10.1109/ISVLSI.2005.69},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/X05a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/XiaZLG05,
author = {Tian Xia and
Hao Zheng and
Jing Li and
Ahmed Ginawi},
title = {Self-Refereed On-Chip Jitter Measurement Circuit Using Vernier Oscillators},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {218--223},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.66},
doi = {10.1109/ISVLSI.2005.66},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/XiaZLG05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/YangAV05,
author = {Huiying Yang and
Anuradha Agarwal and
Ranga Vemuri},
title = {Fast Analog Circuit Synthesis Using Multiparameter Sensitivity Analysis
Based on Element-Coefficient Diagrams},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {71--76},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.33},
doi = {10.1109/ISVLSI.2005.33},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/YangAV05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/YangSHP05,
author = {Guowu Yang and
Xiaoyu Song and
William N. N. Hung and
Marek A. Perkowski},
title = {Bi-Direction Synthesis for Reversible Circuits},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {14--19},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.21},
doi = {10.1109/ISVLSI.2005.21},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/YangSHP05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/YimMK05,
author = {Young Uk Yim and
John F. McDonald and
Russell P. Kraft},
title = {12-23 GHz Ultra Wide Tuning Range Voltage-Controlled Ring Oscillator
with Hybrid Control Schemes},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {278--279},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.1},
doi = {10.1109/ISVLSI.2005.1},
timestamp = {Thu, 29 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/YimMK05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/YuL05,
author = {Zhengtao Yu and
Xun Liu},
title = {Power Analysis of Rotary Clock},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {150--155},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.58},
doi = {10.1109/ISVLSI.2005.58},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/YuL05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ZengH05,
author = {Kaiping Zeng and
Sorin A. Huss},
title = {{RAMS:} {A} {VHDL-AMS} Code Refactoring Tool Supporting High Level
Analog Synthesis},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {266--267},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.60},
doi = {10.1109/ISVLSI.2005.60},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ZengH05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/isvlsi/ZhangNLA05,
author = {Ming Z. Zhang and
Hau T. Ngo and
Adam R. Livingston and
Vijayan K. Asari},
title = {An Efficient {VLSI} Architecture for 2-D Convolution with Quadrant
Symmetric Kernels},
booktitle = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
pages = {303--304},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://doi.org/10.1109/ISVLSI.2005.15},
doi = {10.1109/ISVLSI.2005.15},
timestamp = {Fri, 24 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/isvlsi/ZhangNLA05.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/isvlsi/2005,
title = {2005 {IEEE} Computer Society Annual Symposium on {VLSI} {(ISVLSI}
2005), New Frontiers in {VLSI} Design, 11-12 May 2005, Tampa, FL,
{USA}},
publisher = {{IEEE} Computer Society},
year = {2005},
url = {https://ieeexplore.ieee.org/xpl/conhome/9780/proceeding},
isbn = {0-7695-2365-X},
timestamp = {Wed, 16 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/isvlsi/2005.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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