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@inproceedings{DBLP:conf/isca/AnnavaramGS05,
  author       = {Murali Annavaram and
                  Ed Grochowski and
                  John Paul Shen},
  title        = {Mitigating Amdahl's Law through {EPI} Throttling},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {298--309},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.36},
  doi          = {10.1109/ISCA.2005.36},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/AnnavaramGS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/BaboescuTRS05,
  author       = {Florin Baboescu and
                  Dean M. Tullsen and
                  Grigore Rosu and
                  Sumeet Singh},
  title        = {A Tree Based Router Search Engine Architecture with Single Port Memories},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {123--133},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.7},
  doi          = {10.1109/ISCA.2005.7},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/BaboescuTRS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/BalakrishnanRUL05,
  author       = {Saisanthosh Balakrishnan and
                  Ravi Rajwar and
                  Michael Upton and
                  Konrad K. Lai},
  title        = {The Impact of Performance Asymmetry in Emerging Multicore Architectures},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {506--517},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.51},
  doi          = {10.1109/ISCA.2005.51},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/BalakrishnanRUL05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/BalensieferKO05,
  author       = {Steven Balensiefer and
                  Lucas Kreger{-}Stickles and
                  Mark Oskin},
  title        = {An Evaluation Framework and Instruction Set Architecture for Ion-Trap
                  Based Quantum Micro-Architectures},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {186--196},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.10},
  doi          = {10.1109/ISCA.2005.10},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/BalensieferKO05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/BiswasRCEMR05,
  author       = {Arijit Biswas and
                  Paul Racunas and
                  Razvan Cheveresan and
                  Joel S. Emer and
                  Shubhendu S. Mukherjee and
                  Ram Rangan},
  title        = {Computing Architectural Vulnerability Factors for Address-Based Structures},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {532--543},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.18},
  doi          = {10.1109/ISCA.2005.18},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/BiswasRCEMR05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/CantinLS05,
  author       = {Jason F. Cantin and
                  Mikko H. Lipasti and
                  James E. Smith},
  title        = {Improving Multiprocessor Performance with Coarse-Grain Coherence Tracking},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {246--257},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.31},
  doi          = {10.1109/ISCA.2005.31},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/CantinLS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/ChishtiPV05,
  author       = {Zeshan Chishti and
                  Michael D. Powell and
                  T. N. Vijaykumar},
  title        = {Optimizing Replication, Communication, and Capacity Allocation in
                  CMPs},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {357--368},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.39},
  doi          = {10.1109/ISCA.2005.39},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/ChishtiPV05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/ClarkBCMBF05,
  author       = {Nathan Clark and
                  Jason A. Blome and
                  Michael L. Chu and
                  Scott A. Mahlke and
                  Stuart Biles and
                  Kriszti{\'{a}}n Flautner},
  title        = {An Architecture Framework for Transparent Instruction Set Customization
                  in Embedded Processors},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {272--283},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.9},
  doi          = {10.1109/ISCA.2005.9},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/ClarkBCMBF05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/GandhiARSL05,
  author       = {Amit Gandhi and
                  Haitham Akkary and
                  Ravi Rajwar and
                  Srikanth T. Srinivasan and
                  Konrad K. Lai},
  title        = {Scalable Load and Store Processing in Latency Tolerant Processors},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {446--457},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.46},
  doi          = {10.1109/ISCA.2005.46},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/GandhiARSL05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/GomaaV05,
  author       = {Mohamed A. Gomaa and
                  T. N. Vijaykumar},
  title        = {Opportunistic Transient-Fault Detection},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {172--183},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.38},
  doi          = {10.1109/ISCA.2005.38},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/GomaaV05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/GunawiAAAS05,
  author       = {Haryadi S. Gunawi and
                  Nitin Agrawal and
                  Andrea C. Arpaci{-}Dusseau and
                  Remzi H. Arpaci{-}Dusseau and
                  Jiri Schindler},
  title        = {Deconstructing Commodity Storage Clusters},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {60--71},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.20},
  doi          = {10.1109/ISCA.2005.20},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/GunawiAAAS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/GurumurthiSN05,
  author       = {Sudhanva Gurumurthi and
                  Anand Sivasubramaniam and
                  Vivek K. Natarajan},
  title        = {Disk Drive Roadmap from the Thermal Perspective: {A} Case for Dynamic
                  Thermal Management},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {38--49},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.24},
  doi          = {10.1109/ISCA.2005.24},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/GurumurthiSN05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/HempsteadTMWB05,
  author       = {Mark Hempstead and
                  Nikhil Tripathi and
                  Patrick Mauro and
                  Gu{-}Yeon Wei and
                  David M. Brooks},
  title        = {An Ultra Low Power System Architecture for Sensor Network Applications},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {208--219},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.12},
  doi          = {10.1109/ISCA.2005.12},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/HempsteadTMWB05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/HinesGTW05,
  author       = {Stephen Hines and
                  Joshua Green and
                  Gary S. Tyson and
                  David B. Whalley},
  title        = {Improving Program Efficiency by Packing Instructions into Registers},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {260--271},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.32},
  doi          = {10.1109/ISCA.2005.32},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/HinesGTW05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/HuggahalliIT05,
  author       = {Ram Huggahalli and
                  Ravi R. Iyer and
                  Scott Tetrick},
  title        = {Direct Cache Access for High Bandwidth Network {I/O}},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {50--59},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.23},
  doi          = {10.1109/ISCA.2005.23},
  timestamp    = {Mon, 15 May 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/HuggahalliIT05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/Jimenez05,
  author       = {Daniel A. Jim{\'{e}}nez},
  title        = {Piecewise Linear Branch Prediction},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {382--393},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.40},
  doi          = {10.1109/ISCA.2005.40},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/Jimenez05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/KimDTG05,
  author       = {John Kim and
                  William J. Dally and
                  Brian Towles and
                  Amit K. Gupta},
  title        = {Microarchitecture of a High-Radix Router},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {420--431},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.35},
  doi          = {10.1109/ISCA.2005.35},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/KimDTG05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/KumarZT05,
  author       = {Rakesh Kumar and
                  Victor V. Zyuban and
                  Dean M. Tullsen},
  title        = {Interconnections in Multi-Core Architectures: Understanding Mechanisms,
                  Overheads and Scaling},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {408--419},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.34},
  doi          = {10.1109/ISCA.2005.34},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/KumarZT05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/KyoOA05,
  author       = {Shorin Kyo and
                  Shin'ichiro Okazaki and
                  Tamio Arai},
  title        = {An Integrated Memory Array Processor Architecture for Embedded Image
                  Recognition Systems},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {134--145},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.11},
  doi          = {10.1109/ISCA.2005.11},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/KyoOA05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/LeeKMDW05,
  author       = {Ruby B. Lee and
                  Peter C. S. Kwan and
                  John Patrick McGregor and
                  Jeffrey S. Dwoskin and
                  Zhenghong Wang},
  title        = {Architecture for Protecting Critical Secrets in Microprocessors},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {2--13},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.14},
  doi          = {10.1109/ISCA.2005.14},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/LeeKMDW05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/MeixnerS05,
  author       = {Albert Meixner and
                  Daniel J. Sorin},
  title        = {Dynamic Verification of Sequential Consistency},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {482--493},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.25},
  doi          = {10.1109/ISCA.2005.25},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/MeixnerS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/Moshovos05,
  author       = {Andreas Moshovos},
  title        = {RegionScout: Exploiting Coarse Grain Sharing in Snoop-Based Coherence},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {234--245},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.42},
  doi          = {10.1109/ISCA.2005.42},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/Moshovos05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/MutluKP05,
  author       = {Onur Mutlu and
                  Hyesoon Kim and
                  Yale N. Patt},
  title        = {Techniques for Efficient Processing in Runahead Execution Engines},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {370--381},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.49},
  doi          = {10.1109/ISCA.2005.49},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/MutluKP05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/NarayanasamyPC05,
  author       = {Satish Narayanasamy and
                  Gilles Pokam and
                  Brad Calder},
  title        = {BugNet: Continuously Recording Program Execution for Deterministic
                  Replay Debugging},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {284--295},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.16},
  doi          = {10.1109/ISCA.2005.16},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/NarayanasamyPC05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/NazhandaliZORMHPAB05,
  author       = {Leyla Nazhandali and
                  Bo Zhai and
                  Javin Olson and
                  Anna Reeves and
                  Michael Minuth and
                  Ryan Helfand and
                  Sanjay Pant and
                  Todd M. Austin and
                  David T. Blaauw},
  title        = {Energy Optimization of Subthreshold-Voltage Sensor Network Processors},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {197--207},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.26},
  doi          = {10.1109/ISCA.2005.26},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/NazhandaliZORMHPAB05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/PetricR05,
  author       = {Vlad Petric and
                  Amir Roth},
  title        = {Energy-Effectiveness of Pre-Execution and Energy-Aware P-Thread Selection},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {322--333},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.27},
  doi          = {10.1109/ISCA.2005.27},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/PetricR05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/QureshiTP05,
  author       = {Moinuddin K. Qureshi and
                  David Thompson and
                  Yale N. Patt},
  title        = {The V-Way Cache: Demand Based Associativity via Global Replacement},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {544--555},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.52},
  doi          = {10.1109/ISCA.2005.52},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/QureshiTP05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/RajwarHL05,
  author       = {Ravi Rajwar and
                  Maurice Herlihy and
                  Konrad K. Lai},
  title        = {Virtualizing Transactional Memory},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {494--505},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.54},
  doi          = {10.1109/ISCA.2005.54},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/RajwarHL05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/ReisCVRAM05,
  author       = {George A. Reis and
                  Jonathan Chang and
                  Neil Vachharajani and
                  Ram Rangan and
                  David I. August and
                  Shubhendu S. Mukherjee},
  title        = {Design and Evaluation of Hybrid Fault-Detection Systems},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {148--159},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.21},
  doi          = {10.1109/ISCA.2005.21},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/ReisCVRAM05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/Roth05,
  author       = {Amir Roth},
  title        = {Store Vulnerability Window {(SVW):} Re-Execution Filtering for Enhanced
                  Load Optimization},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {458--468},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.48},
  doi          = {10.1109/ISCA.2005.48},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/Roth05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/SchuchmanV05,
  author       = {Ethan Schuchman and
                  T. N. Vijaykumar},
  title        = {Rescue: {A} Microarchitecture for Testability and Defect Tolerance},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {160--171},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.44},
  doi          = {10.1109/ISCA.2005.44},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/SchuchmanV05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/SeoALRT05,
  author       = {Daeho Seo and
                  Akif Ali and
                  Won{-}Taek Lim and
                  Nauman Rafique and
                  Mithuna Thottethodi},
  title        = {Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh
                  Networks},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {432--443},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.37},
  doi          = {10.1109/ISCA.2005.37},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/SeoALRT05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/Seznec05,
  author       = {Andr{\'{e}} Seznec},
  title        = {Analysis of the O-GEometric History Length Branch Predictor},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {394--405},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.13},
  doi          = {10.1109/ISCA.2005.13},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/Seznec05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/ShiLGLB05,
  author       = {Weidong Shi and
                  Hsien{-}Hsin S. Lee and
                  Mrinmoy Ghosh and
                  Chenghuai Lu and
                  Alexandra Boldyreva},
  title        = {High Efficiency Counter Mode Security Architecture via Prediction
                  and Precomputation},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {14--24},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.30},
  doi          = {10.1109/ISCA.2005.30},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/ShiLGLB05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/SpeightSZR05,
  author       = {Evan Speight and
                  Hazim Shafi and
                  Lixin Zhang and
                  Ramakrishnan Rajamony},
  title        = {Adaptive Mechanisms and Policies for Managing Cache Hierarchies in
                  Chip Multiprocessors},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {346--356},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.8},
  doi          = {10.1109/ISCA.2005.8},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/SpeightSZR05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/SrinivasanABR05,
  author       = {Jayanth Srinivasan and
                  Sarita V. Adve and
                  Pradip Bose and
                  Jude A. Rivers},
  title        = {Exploiting Structural Duplication for Lifetime Reliability Enhancement},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {520--531},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.28},
  doi          = {10.1109/ISCA.2005.28},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/SrinivasanABR05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/SuhOSD05,
  author       = {G. Edward Suh and
                  Charles W. O'Donnell and
                  Ishan Sachdev and
                  Srinivas Devadas},
  title        = {Design and Implementation of the {AEGIS} Single-Chip Secure Processor
                  Using Physical Random Functions},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {25--36},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.22},
  doi          = {10.1109/ISCA.2005.22},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/SuhOSD05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/TalpesM05,
  author       = {Emil Talpes and
                  Diana Marculescu},
  title        = {Increased Scalability and Power Efficiency by Using Multiple Speed
                  Pipelines},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {310--321},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.33},
  doi          = {10.1109/ISCA.2005.33},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/TalpesM05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/TanS05,
  author       = {Lin Tan and
                  Timothy Sherwood},
  title        = {A High Throughput String Matching Architecture for Intrusion Detection
                  and Prevention},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {112--122},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.5},
  doi          = {10.1109/ISCA.2005.5},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/TanS05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/TorresIVL05,
  author       = {Enrique F. Torres and
                  Pablo Ib{\'{a}}{\~{n}}ez and
                  V{\'{\i}}ctor Vi{\~{n}}als and
                  Jos{\'{e}} Mar{\'{\i}}a Llaber{\'{\i}}a},
  title        = {Store Buffer Design in First-Level Multibanked Data Caches},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {469--480},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.47},
  doi          = {10.1109/ISCA.2005.47},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/TorresIVL05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/WenischSHKAF05,
  author       = {Thomas F. Wenisch and
                  Stephen Somogyi and
                  Nikolaos Hardavellas and
                  Jangwoo Kim and
                  Anastassia Ailamaki and
                  Babak Falsafi},
  title        = {Temporal Streaming of Shared Memory},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {222--233},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.50},
  doi          = {10.1109/ISCA.2005.50},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/WenischSHKAF05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/X05,
  author       = {Magnus Ekman and
                  Per Stenstr{\"{o}}m},
  title        = {A Robust Main-Memory Compression Scheme},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {74--85},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.6},
  doi          = {10.1109/ISCA.2005.6},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/X05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/X05a,
  author       = {Brian Fahs and
                  Todd M. Rafacz and
                  Sanjay J. Patel and
                  Steven S. Lumetta},
  title        = {Continuous Optimization},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {86--97},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.19},
  doi          = {10.1109/ISCA.2005.19},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/X05a.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/X05b,
  author       = {Vlad Petric and
                  Tingting Sha and
                  Amir Roth},
  title        = {{RENO} - {A} Rename-Based Instruction Optimizer},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {98--109},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.43},
  doi          = {10.1109/ISCA.2005.43},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/X05b.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/isca/ZhangA05,
  author       = {Michael Zhang and
                  Krste Asanovic},
  title        = {Victim Replication: Maximizing Capacity while Hiding Wire Delay in
                  Tiled Chip Multiprocessors},
  booktitle    = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  pages        = {336--345},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://doi.org/10.1109/ISCA.2005.53},
  doi          = {10.1109/ISCA.2005.53},
  timestamp    = {Fri, 24 Mar 2023 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/isca/ZhangA05.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/isca/2005,
  title        = {32st International Symposium on Computer Architecture {(ISCA} 2005),
                  4-8 June 2005, Madison, Wisconsin, {USA}},
  publisher    = {{IEEE} Computer Society},
  year         = {2005},
  url          = {https://ieeexplore.ieee.org/xpl/conhome/9793/proceeding},
  isbn         = {978-0-7695-2270-8},
  timestamp    = {Fri, 09 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/isca/2005.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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