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@inproceedings{DBLP:conf/fpga/CarrilloC01,
  author       = {Jorge E. Carrillo and
                  Paul Chow},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {The effect of reconfigurable units in superscalar processors},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {141--150},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360328},
  doi          = {10.1145/360276.360328},
  timestamp    = {Tue, 06 Nov 2018 16:58:22 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/CarrilloC01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/ChenC01,
  author       = {Gang Chen and
                  Jason Cong},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Simultaneous logic decomposition with technology mapping in {FPGA}
                  designs},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {48--55},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360298},
  doi          = {10.1145/360276.360298},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/ChenC01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/ChenCEH01,
  author       = {Deming Chen and
                  Jason Cong and
                  Milos D. Ercegovac and
                  Zhijun Huang},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Performance-driven mapping for {CPLD} architectures},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {39--47},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360296},
  doi          = {10.1145/360276.360296},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/ChenCEH01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/ChodowiecKG01,
  author       = {Pawel Chodowiec and
                  Po Khuon and
                  Kris Gaj},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Fast implementations of secret-key block ciphers using mixed inner-
                  and outer-round pipelining},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {94--102},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360309},
  doi          = {10.1145/360276.360309},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/ChodowiecKG01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/DandalisP01,
  author       = {Andreas Dandalis and
                  Viktor K. Prasanna},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Configuration compression for FPGA-based embedded systems},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {173--182},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360342},
  doi          = {10.1145/360276.360342},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/DandalisP01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/EstlickLTS01,
  author       = {Mike Estlick and
                  Miriam Leeser and
                  James Theiler and
                  John J. Szymanski},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Algorithmic transformations in the implementation of {K-} means clustering
                  on reconfigurable hardware},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {103--110},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360311},
  doi          = {10.1145/360276.360311},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/EstlickLTS01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/FrigoGL01,
  author       = {Janette Frigo and
                  Maya B. Gokhale and
                  Dominique Lavenier},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Evaluation of the streams-C C-to-FPGA compiler: an applications perspective},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {134--140},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360326},
  doi          = {10.1145/360276.360326},
  timestamp    = {Mon, 20 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/fpga/FrigoGL01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/HallschmidW01,
  author       = {Peter Hallschmid and
                  Steven J. E. Wilton},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Detailed routing architectures for embedded programmable logic {IP}
                  cores},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {69--74},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360300},
  doi          = {10.1145/360276.360300},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/HallschmidW01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/HuangM01,
  author       = {Wei{-}Je Huang and
                  Edward J. McCluskey},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {A memory coherence technique for online transient error recovery of
                  {FPGA} configurations},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {183--192},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360344},
  doi          = {10.1145/360276.360344},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/HuangM01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/KaptanogluEGHTTV01,
  author       = {Sinan Kaptanoglu and
                  John East and
                  Tim Garverick and
                  Scott Hauck and
                  Tavana Tavana and
                  Steven Trimberger and
                  Ronnie Vasishta},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Is marriage in the cards for programmable logic, microprocessors and
                  ASICs?},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {111},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360313},
  doi          = {10.1145/360276.360313},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/KaptanogluEGHTTV01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/LeeW01,
  author       = {K. K. Lee and
                  D. F. Wong},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {LRoute: a delay minimal router for hierarchical CPLDs},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {12--20},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360290},
  doi          = {10.1145/360276.360290},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/fpga/LeeW01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/LemieuxL01,
  author       = {Guy G. Lemieux and
                  David M. Lewis},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Using sparse crossbars within {LUT}},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {59--68},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360299},
  doi          = {10.1145/360276.360299},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/LemieuxL01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/LienhartMNL01,
  author       = {Gerhard Lienhart and
                  Reinhard M{\"{a}}nner and
                  Klaus{-}Henning Noffz and
                  Ralf Lay},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {An FPGA-based video compressor for {H.263} compatible bit streams},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {207--212},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360356},
  doi          = {10.1145/360276.360356},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/LienhartMNL01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/LockwoodNTT01,
  author       = {John W. Lockwood and
                  Naji Naufel and
                  Jonathan S. Turner and
                  David E. Taylor},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Reprogrammable network packet processing on the field programmable
                  port extender {(FPX)}},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {87--93},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360304},
  doi          = {10.1145/360276.360304},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/LockwoodNTT01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/MoissetDP01,
  author       = {Pablo Moisset and
                  Pedro C. Diniz and
                  Joonseok Park},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Matching and searching analysis for parallel hardware implementation
                  on FPGAs},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {125--133},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360324},
  doi          = {10.1145/360276.360324},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/MoissetDP01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/MulpuriH01,
  author       = {Chandra Mulpuri and
                  Scott Hauck},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Runtime and quality tradeoffs in {FPGA} placement and routing},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {29--36},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360294},
  doi          = {10.1145/360276.360294},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/MulpuriH01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/RamachandranS01,
  author       = {Seetharaman Ramachandran and
                  S. Srinivasan},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {{FPGA} implementation of a novel, fast motion estimation algorithm
                  for real-time video compression},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {213--219},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360358},
  doi          = {10.1145/360276.360358},
  timestamp    = {Fri, 15 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/RamachandranS01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/RitterM01,
  author       = {J{\"{o}}rg Ritter and
                  Paul Molitor},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {A pipelined architecture for partitioned {DWT} based lossy image compression
                  using FPGA's},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {201--206},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360350},
  doi          = {10.1145/360276.360350},
  timestamp    = {Wed, 02 Dec 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/RitterM01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/ShengR01,
  author       = {Mike Sheng and
                  Jonathan Rose},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Mixing buffers and pass transistors in {FPGA} routing architectures},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {75--84},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360302},
  doi          = {10.1145/360276.360302},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/ShengR01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/SinghB01,
  author       = {Deshanand P. Singh and
                  Stephen Dean Brown},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {The case for registered routing switches in field programmable gate
                  arrays},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {161--169},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360331},
  doi          = {10.1145/360276.360331},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/SinghB01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/SinghMM01,
  author       = {Amit Singh and
                  Arindam Mukherjee and
                  Malgorzata Marek{-}Sadowska},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Interconnect pipelining in a throughput-intensive {FPGA} architecture},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {153--160},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360323},
  doi          = {10.1145/360276.360323},
  timestamp    = {Mon, 05 Jun 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/fpga/SinghMM01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/SniderSC01,
  author       = {Greg Snider and
                  Barry Shackleford and
                  Richard J. Carter},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Attacking the semantic gap between application programming languages
                  and configurable hardware},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {115--124},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360322},
  doi          = {10.1145/360276.360322},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/SniderSC01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/SundararajanG01,
  author       = {Prasanna Sundararajan and
                  Steve Guccione},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Run-Time defect tolerance using JBits},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {193--198},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360346},
  doi          = {10.1145/360276.360346},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/SundararajanG01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/fpga/Wilton01,
  author       = {Steven J. E. Wilton},
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {A crosstalk-aware timing-driven router for FPGAs},
  booktitle    = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  pages        = {21--28},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276.360292},
  doi          = {10.1145/360276.360292},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/Wilton01.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/fpga/2001,
  editor       = {Scott Hauck and
                  Martine D. F. Schlag and
                  Russell Tessier},
  title        = {Proceedings of the {ACM/SIGDA} International Symposium on Field Programmable
                  Gate Arrays, {FPGA} 2001, Monterey, CA, USA, February 11-13, 2001},
  publisher    = {{ACM}},
  year         = {2001},
  url          = {https://doi.org/10.1145/360276},
  doi          = {10.1145/360276},
  isbn         = {1-58113-341-3},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/fpga/2001.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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