Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSearch dblp for Publications
export results for "toc:db/conf/cases/cases2014.bht:"
download as .bib file
@inproceedings{DBLP:conf/cases/BelhadjVVDHT14,
author = {Bilel Belhadj and
Alexandre Valentian and
Pascal Vivet and
Marc Duranton and
Liqiang He and
Olivier Temam},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {The improbable but highly appropriate marriage of 3D stacking and
neuromorphic accelerators},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {1:1--1:9},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656130},
doi = {10.1145/2656106.2656130},
timestamp = {Mon, 15 May 2023 22:11:16 +0200},
biburl = {https://dblp.org/rec/conf/cases/BelhadjVVDHT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/ChandramohanO14,
author = {Kiran Chandramohan and
Michael F. P. O'Boyle},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {A compiler framework for automatically mapping data parallel programs
to heterogeneous MPSoCs},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {9:1--9:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656107},
doi = {10.1145/2656106.2656107},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/ChandramohanO14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/DardaillonMRMC14,
author = {Micka{\"{e}}l Dardaillon and
Kevin Marquet and
Tanguy Risset and
J{\'{e}}r{\^{o}}me Martin and
Henri{-}Pierre Charles},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {A compilation flow for parametric dataflow: Programming model, scheduling,
and application to heterogeneous MPSoC},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {8:1--8:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656110},
doi = {10.1145/2656106.2656110},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/DardaillonMRMC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/GrudnitskyBH14,
author = {Artjom Grudnitsky and
Lars Bauer and
J{\"{o}}rg Henkel},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {{COREFAB:} Concurrent reconfigurable fabric utilization in heterogeneous
multi-core systems},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {5:1--5:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656119},
doi = {10.1145/2656106.2656119},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/GrudnitskyBH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/HaabBH14,
author = {Martin Haa{\ss} and
Lars Bauer and
J{\"{o}}rg Henkel},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Automatic custom instruction identification in memory streaming algorithms},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {6:1--6:9},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656114},
doi = {10.1145/2656106.2656114},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/HaabBH14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/HeppB14,
author = {Stefan Hepp and
Florian Brandner},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Splitting functions into single-entry regions},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {17:1--17:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656128},
doi = {10.1145/2656106.2656128},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/HeppB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/HoltonBSR14,
author = {Bryce Holton and
Ke Bai and
Aviral Shrivastava and
Harini Ramaprasad},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Construction of {GCCFG} for inter-procedural optimizations in Software
Managed Manycore {(SMM)} architectures},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {18:1--18:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656122},
doi = {10.1145/2656106.2656122},
timestamp = {Thu, 27 Jul 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/HoltonBSR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/HuDHC14,
author = {Kai Hu and
Trung Anh Dinh and
Tsung{-}Yi Ho and
Krishnendu Chakrabarty},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Control-layer optimization for flow-based mVLSI microfluidic biochips},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {16:1--16:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656118},
doi = {10.1145/2656106.2656118},
timestamp = {Tue, 02 Mar 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/HuDHC14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/HuangHTICW14,
author = {Jing Huang and
Yuanjie Huang and
Olivier Temam and
Paolo Ienne and
Yunji Chen and
Chengyong Wu},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {A low-cost memory interface for high-throughput accelerators},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {11:1--11:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656109},
doi = {10.1145/2656106.2656109},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/HuangHTICW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/KimLWMMP14,
author = {Ryan Gary Kim and
Guangshuo Liu and
Paul Wettin and
Radu Marculescu and
Diana Marculescu and
Partha Pratim Pande},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Energy-efficient VFI-partitioned multicore design using wireless NoC
architectures},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {3:1--3:9},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656120},
doi = {10.1145/2656106.2656120},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/KimLWMMP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/LuPGR14,
author = {Qining Lu and
Karthik Pattabiraman and
Meeta Sharma Gupta and
Jude A. Rivers},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {SDCTune: {A} model for predicting the {SDC} proneness of an application
for configurable protection},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {23:1--23:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656127},
doi = {10.1145/2656106.2656127},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/LuPGR14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/MiniskarKPY14,
author = {Narasinga Rao Miniskar and
Soma Kohli and
Haewoo Park and
Donghoon Yoo},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Retargetable automatic generation of compound instructions for {CGRA}
based reconfigurable processor applications},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {4:1--4:9},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656125},
doi = {10.1145/2656106.2656125},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/MiniskarKPY14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/Nasre14,
author = {Rupesh Nasre},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Auto-parallelization of data structure operations for GPUs},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {7:1--7:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656115},
doi = {10.1145/2656106.2656115},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/Nasre14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/OttlikSVRB14,
author = {Sebastian Ottlik and
Stefan Stattelmann and
Alexander Viehl and
Wolfgang Rosenstiel and
Oliver Bringmann},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Context-sensitive timing simulation of binary embedded software},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {14:1--14:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656117},
doi = {10.1145/2656106.2656117},
timestamp = {Fri, 29 Mar 2019 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/OttlikSVRB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/PallisterEHB14,
author = {James Pallister and
Kerstin Eder and
Simon J. Hollis and
Jeremy Bennett},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {A high-level model of embedded flash energy consumption},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {20:1--20:9},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656108},
doi = {10.1145/2656106.2656108},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/PallisterEHB14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/QuanP14,
author = {Wei Quan and
Andy D. Pimentel},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {A system-level simulation framework for evaluating task migration
in MPSoCs},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {13:1--13:9},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656111},
doi = {10.1145/2656106.2656111},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/QuanP14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/RoyMW14,
author = {Pooja Roy and
Manmohan Manoharan and
Weng{-}Fai Wong},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {EnVM: Virtual memory design for new memory architectures},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {12:1--12:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656121},
doi = {10.1145/2656106.2656121},
timestamp = {Mon, 26 Jun 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/RoyMW14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/SchorBYT14,
author = {Lars Schor and
Iuliana Bacivarov and
Hoeseok Yang and
Lothar Thiele},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {AdaPNet: Adapting process networks in response to resource variations},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {22:1--22:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656112},
doi = {10.1145/2656106.2656112},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/SchorBYT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/SchuchhardtJAKM14,
author = {Matthew Schuchhardt and
Susmit Jha and
Raid Ayoub and
Michael Kishinevsky and
Gokhan Memik},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {{CAPED:} Context-aware personalized display brightness for mobile
devices},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {19:1--19:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656116},
doi = {10.1145/2656106.2656116},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/SchuchhardtJAKM14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/ShiWLZBVX14,
author = {Weidong Shi and
Yuanfeng Wen and
Ziyi Liu and
Xi Zhao and
Dainis Boumber and
Ricardo Vilalta and
Lei Xu},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Fault resilient physical neural networks on a single chip},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {24:1--24:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656126},
doi = {10.1145/2656106.2656126},
timestamp = {Thu, 03 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/ShiWLZBVX14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/StilkerichTEDWS14,
author = {Isabella Stilkerich and
Philip Taffner and
Christoph Erhardt and
Christian Dietrich and
Christian Wawersich and
Michael Stilkerich},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Team up: Cooperative memory management in embedded systems},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {10:1--10:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656129},
doi = {10.1145/2656106.2656129},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/StilkerichTEDWS14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/ViitanenKJT14,
author = {Timo Viitanen and
Heikki Kultala and
Pekka J{\"{a}}{\"{a}}skel{\"{a}}inen and
Jarmo Takala},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Heuristics for greedy transport triggered architecture interconnect
exploration},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {2:1--2:7},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656123},
doi = {10.1145/2656106.2656123},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/conf/cases/ViitanenKJT14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/WagstaffSF14,
author = {Harry Wagstaff and
Tom Spink and
Bj{\"{o}}rn Franke},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Automated {ISA} branch coverage analysis and test case generation
for retargetable instruction set simulators},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {15:1--15:10},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656113},
doi = {10.1145/2656106.2656113},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/WagstaffSF14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/cases/WenZ14,
author = {Hao Wen and
Wei Zhang},
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {Reducing cache leakage energy for hybrid SPM-cache architectures},
booktitle = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
pages = {21:1--21:9},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106.2656124},
doi = {10.1145/2656106.2656124},
timestamp = {Thu, 04 Apr 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/WenZ14.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/cases/2014,
editor = {Karam S. Chatha and
Rolf Ernst and
Anand Raghunathan and
Ravishankar R. Iyer},
title = {2014 International Conference on Compilers, Architecture and Synthesis
for Embedded Systems, {CASES} 2014, Uttar Pradesh, India, October
12-17, 2014},
publisher = {{ACM}},
year = {2014},
url = {https://doi.org/10.1145/2656106},
doi = {10.1145/2656106},
isbn = {978-1-4503-3050-3},
timestamp = {Mon, 15 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/conf/cases/2014.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
retrieved on 2024-05-03 16:14 CEST from data curated by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
