Search dblp for Publications

export results for "toc:db/journals/vlsisp/vlsisp13.bht:"

 download as .bib file

@article{DBLP:journals/vlsisp/AgrawalHKST96,
  author       = {Prathima Agrawal and
                  Eoin Hyden and
                  Paul Krzyzanowski and
                  Mani B. Srivastava and
                  John A. Trotter},
  title        = {Hardware-software architecture of the {SWAN} Wireless {ATM} network},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {2-3},
  pages        = {87--104},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF01130400},
  doi          = {10.1007/BF01130400},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/AgrawalHKST96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/BorahNVOI96,
  author       = {Manjit Borah and
                  Chetana Nagendra and
                  Mohan Vishwanath and
                  Robert Michael Owens and
                  Mary Jane Irwin},
  title        = {An optimal time multiplication free algorithm for edge detection on
                  a mesh},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {1},
  pages        = {67--75},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00930668},
  doi          = {10.1007/BF00930668},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BorahNVOI96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/BurdB96,
  author       = {Thomas D. Burd and
                  Robert W. Brodersen},
  title        = {Processor design for portable systems},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {2-3},
  pages        = {203--221},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF01130406},
  doi          = {10.1007/BF01130406},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/BurdB96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ChandrakasanB96,
  author       = {Anantha P. Chandrakasan and
                  Robert W. Brodersen},
  title        = {Guest editors' introduction},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {2-3},
  pages        = {85--86},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF01130399},
  doi          = {10.1007/BF01130399},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ChandrakasanB96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ChianCJLMPS96,
  author       = {Mojy Chian and
                  Gregg Croft and
                  Steve Jost and
                  Patrick Landy and
                  Brent A. Myers and
                  John Prentice and
                  Doug Schultz},
  title        = {{IC} implementation challenges of a 2.4 GHz wireless {LAN} chipset},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {2-3},
  pages        = {143--163},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF01130403},
  doi          = {10.1007/BF01130403},
  timestamp    = {Tue, 01 Mar 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ChianCJLMPS96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/ChienNLMSBCDMJ96,
  author       = {Charles Chien and
                  Sean Nazareth and
                  Paul Lettieri and
                  Stephen Molloy and
                  Brian Schoner and
                  Walter A. Boring IV and
                  Joey Chen and
                  Christopher Deng and
                  William H. Mangione{-}Smith and
                  Rajeev Jain},
  title        = {An integrated testbed for wireless multimedia computing},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {2-3},
  pages        = {105--124},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF01130401},
  doi          = {10.1007/BF01130401},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/ChienNLMSBCDMJ96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/DiamantarasCK96,
  author       = {Konstantinos I. Diamantaras and
                  W. H. Chou and
                  Sun{-}Yuan Kung},
  title        = {Dynamic programming implementation on array processor architectures},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {1},
  pages        = {27--35},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00930665},
  doi          = {10.1007/BF00930665},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/DiamantarasCK96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/GordonTM96,
  author       = {Benjamin M. Gordon and
                  Ely K. Tsern and
                  Teresa H. Meng},
  title        = {Design of a low power video decompression chip set for portable applications},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {2-3},
  pages        = {125--142},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF01130402},
  doi          = {10.1007/BF01130402},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/GordonTM96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/IenneCK96,
  author       = {Paolo Ienne and
                  Thierry Cornu and
                  Gary Kuhn},
  title        = {Special-purpose digital hardware for neural networks: An architectural
                  survey},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {1},
  pages        = {5--25},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00930664},
  doi          = {10.1007/BF00930664},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/IenneCK96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/KurodaS96,
  author       = {Tadahiro Kuroda and
                  Takayasu Sakurai},
  title        = {Threshold-Volgage control schemes through substrate-bias for low-power
                  high-speed {CMOS} {LSI} design},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {2-3},
  pages        = {191--201},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF01130405},
  doi          = {10.1007/BF01130405},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/KurodaS96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/KwaiP96,
  author       = {Ding{-}Ming Kwai and
                  Behrooz Parhami},
  title        = {{FFT} computation with linear processor arrays using a data-driven
                  control scheme},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {1},
  pages        = {57--66},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00930667},
  doi          = {10.1007/BF00930667},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/KwaiP96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/MehraGR96,
  author       = {Renu Mehra and
                  Lisa M. Guerra and
                  Jan M. Rabaey},
  title        = {Low-power architectural synthesis and the impact of exploiting locality},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {2-3},
  pages        = {239--258},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF01130408},
  doi          = {10.1007/BF01130408},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/MehraGR96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/MonteiroD96,
  author       = {Jos{\'{e}} Monteiro and
                  Srinivas Devadas},
  title        = {Techniques for power estimation and optimization at the logic level:
                  {A} survey},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {2-3},
  pages        = {259--276},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF01130409},
  doi          = {10.1007/BF01130409},
  timestamp    = {Wed, 23 Feb 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsisp/MonteiroD96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/SarmaA96,
  author       = {Kalluri R. Sarma and
                  Tayo Akinwande},
  title        = {Flat panel displays for portable systems},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {2-3},
  pages        = {165--190},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF01130404},
  doi          = {10.1007/BF01130404},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/SarmaA96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/SheligaS96,
  author       = {Michael Sheliga and
                  Edwin Hsing{-}Mean Sha},
  title        = {Hardware/Software co-design with the {HMS} framework},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {1},
  pages        = {37--56},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF00930666},
  doi          = {10.1007/BF00930666},
  timestamp    = {Wed, 20 May 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/SheligaS96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsisp/TiwariMWL96,
  author       = {Vivek Tiwari and
                  Sharad Malik and
                  Andrew Wolfe and
                  Mike Tien{-}Chien Lee},
  title        = {Instruction level power analysis and optimization of software},
  journal      = {J. {VLSI} Signal Process.},
  volume       = {13},
  number       = {2-3},
  pages        = {223--238},
  year         = {1996},
  url          = {https://doi.org/10.1007/BF01130407},
  doi          = {10.1007/BF01130407},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsisp/TiwariMWL96.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.