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@article{DBLP:journals/vlsi/Chattopadhyay13,
  author       = {Anupam Chattopadhyay},
  title        = {Ingredients of Adaptability: {A} Survey of Reconfigurable Processors},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {683615:1--683615:18},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/683615},
  doi          = {10.1155/2013/683615},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/Chattopadhyay13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ChenCL13,
  author       = {Hou{-}Ming Chen and
                  Robert C. Chang and
                  Kuang{-}Hao Lin},
  title        = {A High-Efficiency Monolithic {DC-DC} {PFM} Boost Converter with Parallel
                  Power {MOS} Technique},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {643293:1--643293:7},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/643293},
  doi          = {10.1155/2013/643293},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/ChenCL13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/Cheng13,
  author       = {Ching{-}Hwa Cheng},
  title        = {Design Example of Useful Memory Latency for Developing a Hazard Preventive
                  Pipeline High-Performance Embedded-Microprocessor},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {425105:1--425105:10},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/425105},
  doi          = {10.1155/2013/425105},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/Cheng13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ChisaguanoO13,
  author       = {Diego Javier Reinoso Chisaguano and
                  Minoru Okada},
  title        = {Low Complexity Submatrix Divided {MMSE} Sparse-SQRD Detection for
                  {MIMO-OFDM} with {ESPAR} Antenna Receiver},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {206909:1--206909:11},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/206909},
  doi          = {10.1155/2013/206909},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/ChisaguanoO13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ChuYH13,
  author       = {Ting{-}Li Chu and
                  Sin{-}Hong Yu and
                  Chorng{-}Sii Hwang},
  title        = {High-Accuracy Programmable Timing Generator with Wide-Range Tuning
                  Capability},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {803616:1--803616:6},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/803616},
  doi          = {10.1155/2013/803616},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/ChuYH13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ColonnaGCGZ13,
  author       = {Francesco Colonna and
                  Mariagrazia Graziano and
                  Mario Roberto Casu and
                  Xiaolu Guo and
                  Maurizio Zamboni},
  title        = {Hardware Acceleration of Beamforming in a {UWB} Imaging Unit for Breast
                  Cancer Detection},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {861691:1--861691:11},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/861691},
  doi          = {10.1155/2013/861691},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/ColonnaGCGZ13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/ElhossiniAD13,
  author       = {Ahmed Elhossini and
                  Shawki Areibi and
                  Robert D. Dony},
  title        = {Architecture Exploration Based on {GA-PSO} Optimization, {ANN} Modeling,
                  and Static Scheduling},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {624369:1--624369:22},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/624369},
  doi          = {10.1155/2013/624369},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/ElhossiniAD13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/FanC13,
  author       = {Yu{-}Cheng Fan and
                  Yi{-}Feng Chiang},
  title        = {Discrete Wavelet Transform on Color Picture Interpolation of Digital
                  Still Camera},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {738057:1--738057:9},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/738057},
  doi          = {10.1155/2013/738057},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/FanC13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/HatanakaHO13,
  author       = {Masahide Hatanaka and
                  Toru Homemoto and
                  Takao Onoye},
  title        = {Architecture and Implementation of Fading Compensation for Dynamic
                  Spectrum Access Wireless Communication Systems},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {967370:1--967370:9},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/967370},
  doi          = {10.1155/2013/967370},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/HatanakaHO13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/HoeBM13,
  author       = {David H. K. Hoe and
                  L. P. Deepthi Bollepalli and
                  Chris D. Martinez},
  title        = {{FPGA} Fault Tolerant Arithmetic Logic: {A} Case Study Using Parallel-Prefix
                  Adders},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {382682:1--382682:10},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/382682},
  doi          = {10.1155/2013/382682},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/HoeBM13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/HsiaoSLHHWL13,
  author       = {Yu{-}Ming Hsiao and
                  Miin{-}Shyue Shiau and
                  Kuen{-}Han Li and
                  Jing{-}Jhong Hou and
                  Heng{-}Shou Hsu and
                  Hong{-}Chong Wu and
                  Don{-}Gey Liu},
  title        = {Design a Bioamplifier with High {CMRR}},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {210265:1--210265:5},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/210265},
  doi          = {10.1155/2013/210265},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/HsiaoSLHHWL13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/IwaizumiYM13,
  author       = {Hiroki Iwaizumi and
                  Shingo Yoshizawa and
                  Yoshikazu Miyanaga},
  title        = {A High-Speed and Low-Energy-Consumption Processor for {SVD-MIMO-OFDM}
                  Systems},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {625019:1--625019:10},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/625019},
  doi          = {10.1155/2013/625019},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/IwaizumiYM13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/KumarSDP13,
  author       = {A. Kishore Kumar and
                  D. Somasundareswari and
                  V. Duraisamy and
                  T. Shunbaga Pradeepa},
  title        = {Design of Low Power Multiplier with Energy Efficient Full Adder Using
                  {DPTAAL}},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {157872:1--157872:9},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/157872},
  doi          = {10.1155/2013/157872},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/KumarSDP13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/LiuLW13,
  author       = {Liyuan Liu and
                  Dongmei Li and
                  Zhihua Wang},
  title        = {A 0.6-V to 1-V Audio Delta-Sigma Modulator in 65 nm {CMOS} with 90.2
                  dB {SNDR} at 0.6-V},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {353080:1--353080:9},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/353080},
  doi          = {10.1155/2013/353080},
  timestamp    = {Fri, 30 Jul 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/LiuLW13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MehtaSB13,
  author       = {Dinesh P. Mehta and
                  Carl Shetters and
                  Donald W. Bouldin},
  title        = {Meta-Algorithms for Scheduling a Chain of Coarse-Grained Tasks on
                  an Array of Reconfigurable FPGAs},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {249592:1--249592:13},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/249592},
  doi          = {10.1155/2013/249592},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/vlsi/MehtaSB13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/MohseninSB13,
  author       = {Tinoosh Mohsenin and
                  Houshmand Shirani{-}mehr and
                  Bevan M. Baas},
  title        = {{LDPC} Decoder with an Adaptive Wordwidth Datapath for Energy and
                  {BER} Co-Optimization},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {913018:1--913018:14},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/913018},
  doi          = {10.1155/2013/913018},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/MohseninSB13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/OlivieriM13,
  author       = {Mauro Olivieri and
                  Antonio Mastrandrea},
  title        = {A General Design Methodology for Synchronous Early-Completion-Prediction
                  Adders in Nano-CMOS {DSP} Architectures},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {785281:1--785281:12},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/785281},
  doi          = {10.1155/2013/785281},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/OlivieriM13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/RadojicicGSR13,
  author       = {Carna Radojicic and
                  Christoph Grimm and
                  Florian Schupfer and
                  Michael Rathmair},
  title        = {Verification of Mixed-Signal Systems with Affine Arithmetic Assertions},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {239064:1--239064:14},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/239064},
  doi          = {10.1155/2013/239064},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/RadojicicGSR13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/RamkumarK13,
  author       = {B. Ramkumar and
                  Harish M. Kittur},
  title        = {Faster and Energy-Efficient Signed Multipliers},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {495354:1--495354:12},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/495354},
  doi          = {10.1155/2013/495354},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/RamkumarK13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/RenD13,
  author       = {Huan Ren and
                  Shantanu Dutt},
  title        = {Fast and Near-Optimal Timing-Driven Cell Sizing under Cell Area and
                  Leakage Power Constraints Using a Simplified Discrete Network Flow
                  Algorithm},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {474601:1--474601:15},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/474601},
  doi          = {10.1155/2013/474601},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/RenD13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/SuCW13,
  author       = {Ching{-}Lung Su and
                  Tse{-}Min Chen and
                  Kuo{-}Hsuan Wu},
  title        = {A Prototype-Based Gate-Level Cycle-Accurate Methodology for SoC Performance
                  Exploration and Estimation},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {529150:1--529150:10},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/529150},
  doi          = {10.1155/2013/529150},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/SuCW13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/TafesseM13,
  author       = {Bisrat Tafesse and
                  Venkatesan Muthukumar},
  title        = {Framework for Simulation of Heterogeneous MpSoC for Design Space Exploration},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {936181:1--936181:16},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/936181},
  doi          = {10.1155/2013/936181},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/TafesseM13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/TraboulsiFPHB13,
  author       = {Shadi Traboulsi and
                  Valerio Frascolla and
                  Nils Pohl and
                  Josef Hausner and
                  Attila Bilgic},
  title        = {Energy-Efficient Hardware Architectures for the Packet Data Convergence
                  Protocol in LTE-Advanced Mobile Terminals},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {369627:1--369627:15},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/369627},
  doi          = {10.1155/2013/369627},
  timestamp    = {Mon, 15 Jun 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/TraboulsiFPHB13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/UpadhyayNM13,
  author       = {Shipra Upadhyay and
                  Rajendra Kumar Nagaria and
                  Ram Awadh Mishra},
  title        = {Low-Power Adiabatic Computing with Improved Quasistatic Energy Recovery
                  Logic},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {726324:1--726324:9},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/726324},
  doi          = {10.1155/2013/726324},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/UpadhyayNM13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/WuDL13,
  author       = {Tai{-}Hsuan Wu and
                  Azadeh Davoodi and
                  Jeffrey T. Linderoth},
  title        = {Power-Driven Global Routing for Multisupply Voltage Domains},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {905493:1--905493:12},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/905493},
  doi          = {10.1155/2013/905493},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/WuDL13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/XieE13,
  author       = {Zheng Xie and
                  Doug A. Edwards},
  title        = {Computational Performance Optimisation for Statistical Analysis of
                  the Effect of Nano-CMOS Variability on Integrated Circuits},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {984376:1--984376:22},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/984376},
  doi          = {10.1155/2013/984376},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/XieE13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/vlsi/YenYLH13,
  author       = {Mao{-}Hsu Yen and
                  Chu Yu and
                  Horng{-}Ru Liao and
                  Chin{-}Fa Hsieh},
  title        = {A Generic Three-Sided Rearrangeable Switching Network for Polygonal
                  {FPGA} Design},
  journal      = {{VLSI} Design},
  volume       = {2013},
  pages        = {103473:1--103473:15},
  year         = {2013},
  url          = {https://doi.org/10.1155/2013/103473},
  doi          = {10.1155/2013/103473},
  timestamp    = {Sun, 02 Jun 2019 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/vlsi/YenYLH13.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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