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@article{DBLP:journals/vlsi/AbdallahPGR02,
author = {Naoufel Ben Abdallah and
Olivier Pinaud and
Carl L. Gardner and
Christian A. Ringhofer},
title = {A Comparison of Resonant Tunneling Based on Schr{\"{o}}dinger's
Equation and Quantum Hydrodynamics},
journal = {{VLSI} Design},
volume = {15},
number = {4},
pages = {695--700},
year = {2002},
url = {https://doi.org/10.1080/106551402100012309},
doi = {10.1080/106551402100012309},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/AbdallahPGR02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/AnileH02,
author = {Marcello A. Anile and
Simon D. Hern},
title = {Two-valley Hydrodynamical Models for Electron Transport in Gallium
Arsenide: Simulation of Gunn Oscillations},
journal = {{VLSI} Design},
volume = {15},
number = {4},
pages = {681--693},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012291},
doi = {10.1080/1065514021000012291},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/AnileH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ArunachalamBP02,
author = {Ravishankar Arunachalam and
Ronald DeShawn Blanton and
Lawrence T. Pileggi},
title = {Accurate Coupling-centric Timing Analysis Incorporating Temporal and
Functional Isolation},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {605--618},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012228},
doi = {10.1080/1065514021000012228},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ArunachalamBP02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Ben-AsherS02,
author = {Yosi Ben{-}Asher and
Esti Stein},
title = {Basic Algorithms for the Asynchronous Reconfigurable Mesh},
journal = {{VLSI} Design},
volume = {15},
number = {1},
pages = {441--454},
year = {2002},
url = {https://doi.org/10.1080/106551402100002057},
doi = {10.1080/106551402100002057},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Ben-AsherS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/BickenCS02,
author = {Gurcan Bicken and
Graham F. Carey and
R. O. Stearman},
title = {Frequency Domain Kernel Estimation for 2nd-order Volterra Models Using
Random Multi-tone Excitation},
journal = {{VLSI} Design},
volume = {15},
number = {4},
pages = {701--713},
year = {2002},
url = {https://doi.org/10.1080/106551402100012318},
doi = {10.1080/106551402100012318},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/BickenCS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/BucherM02,
author = {Ralph Bucher and
Durga Misra},
title = {A Synthesizable {VHDL} Model of the Exact Solution for Three-dimensional
Hyperbolic Positioning System},
journal = {{VLSI} Design},
volume = {15},
number = {2},
pages = {507--520},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012129},
doi = {10.1080/1065514021000012129},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/BucherM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/BuflerSZIAF02,
author = {F. M. Bufler and
Andreas Schenk and
Christoph Zechner and
Natsuko Inada and
Yoshinori Asahi and
Wolfgang Fichtner},
title = {Comparison of Single-Particle Monte Carlo Simulation with Measured
Output Characteristics of an 0.1{\(\mathrm{\mu}\)}m n-MOSFET},
journal = {{VLSI} Design},
volume = {15},
number = {4},
pages = {715--720},
year = {2002},
url = {https://doi.org/10.1080/106551402100012327},
doi = {10.1080/106551402100012327},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/BuflerSZIAF02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Chen02,
author = {Chien{-}In Henry Chen},
title = {Timing Analysis and Optimization for {DSM} {IC} - Guest Editorial},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {555--556},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012174},
doi = {10.1080/1065514021000012174},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Chen02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/DhaouPT02,
author = {Imed Ben Dhaou and
Keshab K. Parhi and
Hannu Tenhunen},
title = {Energy Efficient Signaling in Deep-submicron Technology},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {563--586},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012192},
doi = {10.1080/1065514021000012192},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/DhaouPT02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ErdoganA02,
author = {Ahmet Teyfik Erdogan and
Tughrul Arslan},
title = {A Combined Coefficient Segmentation and Block Processing Algorithm
for Low Power Implementation of {FIR} Digital Filters},
journal = {{VLSI} Design},
volume = {15},
number = {2},
pages = {529--535},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012147},
doi = {10.1080/1065514021000012147},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ErdoganA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/FlottesRV02,
author = {Marie{-}Lise Flottes and
Bruno Rouzeyre and
Laurent Volpe},
title = {Improving Datapath Testability by Modifying Controller Specification},
journal = {{VLSI} Design},
volume = {15},
number = {2},
pages = {491--498},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012101},
doi = {10.1080/1065514021000012101},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/FlottesRV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Gardner02,
author = {Carl L. Gardner},
title = {{VLSI} Design Special Issue on Semiconductor Device Modeling},
journal = {{VLSI} Design},
volume = {15},
number = {4},
pages = {679},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012282},
doi = {10.1080/1065514021000012282},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Gardner02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/GardnerGH02,
author = {Carl L. Gardner and
Anne Gelb and
Justin Hernandez},
title = {A Comparison of Modern Hyperbolic Methods for Semiconductor Device
Simulation: {NTK} Central Scheme Vs. {CLAWPACK}},
journal = {{VLSI} Design},
volume = {15},
number = {4},
pages = {721--728},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012336},
doi = {10.1080/1065514021000012336},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/GardnerGH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/HasanW02,
author = {S. M. Rezaul Hasan and
Yufridin Wahab},
title = {Reduction of Power Dissipation in Dynamic BiCMOS Logic Gates by Transistor
Reordering},
journal = {{VLSI} Design},
volume = {15},
number = {2},
pages = {547--553},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012165},
doi = {10.1080/1065514021000012165},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/HasanW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Hsiao02,
author = {Michael S. Hsiao},
title = {Genetic Spot Optimization for Peak Power Estimation in Large {VLSI}
Circuits},
journal = {{VLSI} Design},
volume = {15},
number = {1},
pages = {407--416},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012020},
doi = {10.1080/1065514021000012020},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Hsiao02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/HsiaoYC02,
author = {Shen{-}Fu Hsiao and
Jia{-}Siang Yeh and
Da{-}Yen Chen},
title = {High-performance Multiplexer-based Logic Synthesis Using Pass-transistor
Logic},
journal = {{VLSI} Design},
volume = {15},
number = {1},
pages = {417--426},
year = {2002},
url = {https://doi.org/10.1080/1065514021000054736},
doi = {10.1080/1065514021000054736},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/HsiaoYC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/HuS02,
author = {Jiang Hu and
Sachin S. Sapatnekar},
title = {Performance Driven Global Routing Through Gradual Refinement},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {595--604},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012219},
doi = {10.1080/1065514021000012219},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/HuS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Huang02,
author = {Shi{-}Yu Huang},
title = {Improving the Timing of Extended Finite State Machines Via Catalyst},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {629--635},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012246},
doi = {10.1080/1065514021000012246},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Huang02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/HuangC02,
author = {Johnnie A. Huang and
Chien{-}In Henry Chen},
title = {Timing-Driven-Testable Convergent Tree Adders},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {637--645},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012255},
doi = {10.1080/1065514021000012255},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/HuangC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Jerome02,
author = {Joseph W. Jerome},
title = {An Analytical Study of Smooth Solutions of the Bl{\o}tekj{\ae}r Hydrodynamic
Model of Electron Transport},
journal = {{VLSI} Design},
volume = {15},
number = {4},
pages = {729--742},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012345},
doi = {10.1080/1065514021000012345},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Jerome02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Knowles02,
author = {Greg Knowles},
title = {Hardware Architectures for the Orthogonal and Biorthogonal Wavelet
Transform},
journal = {{VLSI} Design},
volume = {15},
number = {2},
pages = {499--506},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012110},
doi = {10.1080/1065514021000012110},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Knowles02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/LeeCCW02,
author = {Yu{-}Min Lee and
Charlie Chung{-}Ping Chen and
Yao{-}Wen Chang and
Martin D. F. Wong},
title = {Simultaneous Buffer-sizing and Wire-sizing for Clock Trees Based on
Lagrangian Relaxation},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {587--594},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012200},
doi = {10.1080/1065514021000012200},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/LeeCCW02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/LeeG02,
author = {Sangho Lee and
Edwin W. Greeneich},
title = {{CMOS} Delay and Power Model Equations for Simultaneous Transistor
and Interconnect Wire Analysis and Optimization},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {619--628},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012237},
doi = {10.1080/1065514021000012237},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/LeeG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/LimaSCV02,
author = {Jader A. De Lima and
Sidnei F. Silva and
Adriano S. Cordeiro and
Michel Verleysen},
title = {A {CMOS/SOI} Single-input {PWM} Discriminator for Low-voltage Body-implanted
Applications},
journal = {{VLSI} Design},
volume = {15},
number = {1},
pages = {469--476},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012075},
doi = {10.1080/1065514021000012075},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/LimaSCV02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/LinC02,
author = {Ichiang Lin and
Chien{-}In Henry Chen},
title = {Timing Challenges for Very Deep Sub-Micron {(VDSM)} {IC}},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {557--562},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012183},
doi = {10.1080/1065514021000012183},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/LinC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/LuYS02,
author = {Shyue{-}Kung Lu and
Fu{-}Min Yeh and
Jen{-}Sheng Shih},
title = {Fault Detection and Fault Diagnosis Techniques for Lookup Table FPGAs},
journal = {{VLSI} Design},
volume = {15},
number = {1},
pages = {397--406},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012011},
doi = {10.1080/1065514021000012011},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/LuYS02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/MoisiadisBA02,
author = {Yiannis Moisiadis and
Ilias Bouras and
Angela Arapoyanni},
title = {Charge Pump Circuits for Low-voltage Applications},
journal = {{VLSI} Design},
volume = {15},
number = {1},
pages = {477--483},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012084},
doi = {10.1080/1065514021000012084},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/MoisiadisBA02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Ramachandran002,
author = {Seetharaman Ramachandran and
S. Srinivasan},
title = {A Dynamically Reconfigurable Video Compression Scheme Using FPGAs
with Coarse-grain Parallelism},
journal = {{VLSI} Design},
volume = {15},
number = {2},
pages = {521--528},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012138},
doi = {10.1080/1065514021000012138},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Ramachandran002.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/ReRC02,
author = {Marco Re and
Andrea Del Re and
Gian Carlo Cardarilli},
title = {Efficient Implementation of a Demultiplexer Based on a Multirate Filter
Bank for the Skyplex Satellites {DVB} System},
journal = {{VLSI} Design},
volume = {15},
number = {1},
pages = {427--440},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012048},
doi = {10.1080/1065514021000012048},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/ReRC02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/Saab02,
author = {Youssef Saab},
title = {A Contraction-based Ratio-cut Partitioning Algorithm},
journal = {{VLSI} Design},
volume = {15},
number = {2},
pages = {485--489},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012093},
doi = {10.1080/1065514021000012093},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/Saab02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/SaranitiHG02,
author = {Marco Saraniti and
Yibing Hu and
Stephen Marshall Goodnick},
title = {Particle-based Full-band Approach for Fast Simulation of Charge Transport
in Si, GaAs, and InP},
journal = {{VLSI} Design},
volume = {15},
number = {4},
pages = {743--750},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012354},
doi = {10.1080/1065514021000012354},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/SaranitiHG02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/SklavosPTK02,
author = {Nikos Sklavos and
Alexandros Papakonstantinou and
Spyros Theoharis and
Odysseas G. Koufopavlou},
title = {Low-power Implementation of an Encryption/Decryption System with Asynchronous
Techniques},
journal = {{VLSI} Design},
volume = {15},
number = {1},
pages = {455--468},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012066},
doi = {10.1080/1065514021000012066},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/SklavosPTK02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/SulistyoH02,
author = {Jos B. Sulistyo and
Dong Sam Ha},
title = {A New Characterization Method for Delay and Power Dissipation of Standard
Library Cells},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {667--678},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012273},
doi = {10.1080/1065514021000012273},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/SulistyoH02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/WettsteinPL02,
author = {Andreas Wettstein and
Oleg Penzin and
Eugeny D. Lyumkis},
title = {Integration of the Density Gradient Model into a General Purpose Device
Simulator},
journal = {{VLSI} Design},
volume = {15},
number = {4},
pages = {751--759},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012363},
doi = {10.1080/1065514021000012363},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/WettsteinPL02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/WroblewskiSSN02,
author = {Artur Wr{\'{o}}blewski and
Christian V. Schimpfle and
Otto Schumacher and
Josef A. Nossek},
title = {Minimizing Spurious Switching Activities with Transistor Sizing},
journal = {{VLSI} Design},
volume = {15},
number = {2},
pages = {537--545},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012156},
doi = {10.1080/1065514021000012156},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/WroblewskiSSN02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/vlsi/XiaoM02,
author = {Tong Xiao and
Malgorzata Marek{-}Sadowska},
title = {Using Temporal and Functional Information in Crosstalk Aware Static
Timing Analysis},
journal = {{VLSI} Design},
volume = {15},
number = {3},
pages = {647--666},
year = {2002},
url = {https://doi.org/10.1080/1065514021000012264},
doi = {10.1080/1065514021000012264},
timestamp = {Mon, 08 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/vlsi/XiaoM02.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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