Stop the war!Остановите войну!
for scientists:
default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDSearch dblp for Publications
export results for "toc:db/journals/trets/trets11.bht:"
download as .bib file
@article{DBLP:journals/trets/DumpalaPHT19,
author = {Naveen Kumar Dumpala and
Shivukumar B. Patil and
Daniel E. Holcomb and
Russell Tessier},
title = {Loop Unrolling for Energy Efficiency in Low-Cost Field-Programmable
Gate Arrays},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {4},
pages = {26:1--26:23},
year = {2019},
url = {https://doi.org/10.1145/3289186},
doi = {10.1145/3289186},
timestamp = {Fri, 07 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DumpalaPHT19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KrohD19,
author = {Alexander Kroh and
Oliver Diessel},
title = {Efficient Fine-grained Processor-logic Interactions on the Cache-coherent
Zynq Platform},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {4},
pages = {25:1--25:22},
year = {2019},
url = {https://doi.org/10.1145/3277506},
doi = {10.1145/3277506},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/KrohD19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiuZ19,
author = {Gai Liu and
Zhiru Zhang},
title = {PIMap: {A} Flexible Framework for Improving LUT-Based Technology Mapping
via Parallelized Iterative Optimization},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {4},
pages = {23:1--23:23},
year = {2019},
url = {https://doi.org/10.1145/3268344},
doi = {10.1145/3268344},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiuZ19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WangTS19,
author = {Haomiao Wang and
Prabu Thiagaraj and
Oliver Sinnen},
title = {FPGA-based Acceleration of {FT} Convolution for Pulsar Search Using
OpenCL},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {4},
pages = {24:1--24:25},
year = {2019},
url = {https://doi.org/10.1145/3268933},
doi = {10.1145/3268933},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/WangTS19.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/AnandakumarDSH18,
author = {N. Nalla Anandakumar and
M. Prem Laxman Das and
Somitra Kumar Sanadhya and
Mohammad S. Hashmi},
title = {Reconfigurable Hardware Architecture for Authenticated Key Agreement
Protocol Over Binary Edwards Curve},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {2},
pages = {12:1--12:19},
year = {2018},
url = {https://doi.org/10.1145/3231743},
doi = {10.1145/3231743},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/AnandakumarDSH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Bakos18,
author = {Jason D. Bakos},
title = {Introduction to the Special Section on FCCM'16},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
year = {2018},
url = {https://doi.org/10.1145/3183572},
doi = {10.1145/3183572},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Bakos18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BlottPFGOULV18,
author = {Michaela Blott and
Thomas B. Preu{\ss}er and
Nicholas J. Fraser and
Giulio Gambardella and
Kenneth O'Brien and
Yaman Umuroglu and
Miriam Leeser and
Kees A. Vissers},
title = {FINN-\emph{R}: An End-to-End Deep-Learning Framework for Fast Exploration
of Quantized Neural Networks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {16:1--16:23},
year = {2018},
url = {https://doi.org/10.1145/3242897},
doi = {10.1145/3242897},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/BlottPFGOULV18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/BoutrosYB18,
author = {Andrew Boutros and
Sadegh Yazdanshenas and
Vaughn Betz},
title = {You Cannot Improve What You Do not Measure: {FPGA} vs. {ASIC} Efficiency
Gaps for Convolutional Neural Network Inference},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {20:1--20:23},
year = {2018},
url = {https://doi.org/10.1145/3242898},
doi = {10.1145/3242898},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/BoutrosYB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ChenPW18,
author = {Deming Chen and
Andrew Putnam and
Steven J. E. Wilton},
title = {Introduction to the Special Section on Deep Learning in FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {14:1--14:3},
year = {2018},
url = {https://doi.org/10.1145/3294768},
doi = {10.1145/3294768},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ChenPW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DaigneaultD18,
author = {Marc{-}Andr{\'{e}} Daigneault and
Jean{-}Pierre David},
title = {Automated Synthesis of Streaming Transfer Level Hardware Designs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {2},
pages = {13:1--13:22},
year = {2018},
url = {https://doi.org/10.1145/3243930},
doi = {10.1145/3243930},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DaigneaultD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DavisHLSCC18,
author = {James J. Davis and
Eddie Hung and
Joshua M. Levine and
Edward A. Stott and
Peter Y. K. Cheung and
George A. Constantinides},
title = {KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation
for {FPGA} Designs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {2:1--2:22},
year = {2018},
url = {https://doi.org/10.1145/3129789},
doi = {10.1145/3129789},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DavisHLSCC18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/DingLBM18,
author = {Ruizhou Ding and
Zeye Liu and
R. D. (Shawn) Blanton and
Diana Marculescu},
title = {Lightening the Load with Highly Accurate Storage- and Energy-Efficient
LightNNs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {17:1--17:24},
year = {2018},
url = {https://doi.org/10.1145/3270689},
doi = {10.1145/3270689},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/DingLBM18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/GiesenGRKD18,
author = {Hans Giesen and
Benjamin Gojman and
Raphael Rubin and
Ji Kim and
Andr{\'{e}} DeHon},
title = {Continuous Online Self-Monitoring Introspection Circuitry for Timing
Repair by Incremental Partial-Reconfiguration {(COSMIC} {TRIP)}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {3:1--3:23},
year = {2018},
url = {https://doi.org/10.1145/3158229},
doi = {10.1145/3158229},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/GiesenGRKD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KadiJMH18,
author = {Muhammed Al Kadi and
Benedikt Jan{\ss}en and
Jones Yudi Mori and
Michael H{\"{u}}bner},
title = {General-Purpose Computing with Soft GPUs on FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {5:1--5:22},
year = {2018},
url = {https://doi.org/10.1145/3173548},
doi = {10.1145/3173548},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/KadiJMH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/KhanY18,
author = {Farheen Fatima Khan and
Andy Gean Ye},
title = {An Evaluation on the Accuracy of the Minimum-Width Transistor Area
Models in Ranking the Layout Area of {FPGA} Architectures},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {8:1--8:23},
year = {2018},
url = {https://doi.org/10.1145/3182394},
doi = {10.1145/3182394},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/KhanY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/LiuFNNCL18,
author = {Shuanglong Liu and
Hongxiang Fan and
Xinyu Niu and
Ho{-}Cheung Ng and
Yang Chu and
Wayne Luk},
title = {Optimizing CNN-based Segmentation with Deeply Customized Convolutional
and Deconvolutional Architectures on {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {19:1--19:22},
year = {2018},
url = {https://doi.org/10.1145/3242900},
doi = {10.1145/3242900},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/LiuFNNCL18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/MeloniCDBCRRB18,
author = {Paolo Meloni and
Alessandro Capotondi and
Gianfranco Deriu and
Michele Brian and
Francesco Conti and
Davide Rossi and
Luigi Raffo and
Luca Benini},
title = {NEURAghe: Exploiting {CPU-FPGA} Synergies for Efficient and Flexible
{CNN} Inference Acceleration on Zynq SoCs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {18:1--18:24},
year = {2018},
url = {https://doi.org/10.1145/3284357},
doi = {10.1145/3284357},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/MeloniCDBCRRB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/PetelinB18,
author = {Oleg Petelin and
Vaughn Betz},
title = {Wotan: Evaluating {FPGA} Architecture Routability without Benchmarks},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {2},
pages = {11:1--11:23},
year = {2018},
url = {https://doi.org/10.1145/3195800},
doi = {10.1145/3195800},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/PetelinB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/Prost-BoucleBP18,
author = {Adrien Prost{-}Boucle and
Alban Bourge and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot},
title = {High-Efficiency Convolutional Ternary Neural Networks with Custom
Adder Trees and Weight Compression},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {15:1--15:24},
year = {2018},
url = {https://doi.org/10.1145/3270764},
doi = {10.1145/3270764},
timestamp = {Tue, 16 Aug 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/Prost-BoucleBP18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RossiDBBH18,
author = {Enrico Rossi and
Marvin Damschen and
Lars Bauer and
Giorgio C. Buttazzo and
J{\"{o}}rg Henkel},
title = {Preemption of the Partial Reconfiguration Process to Enable Real-Time
Computing With FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {2},
pages = {10:1--10:24},
year = {2018},
url = {https://doi.org/10.1145/3182183},
doi = {10.1145/3182183},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/RossiDBBH18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/RouhaniHLK18,
author = {Bita Darvish Rouhani and
Siam Umar Hussain and
Kristin E. Lauter and
Farinaz Koushanfar},
title = {ReDCrypt: Real-Time Privacy-Preserving Deep Learning Inference in
Clouds Using FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {21:1--21:21},
year = {2018},
url = {https://doi.org/10.1145/3242899},
doi = {10.1145/3242899},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/RouhaniHLK18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/StewartDMGBW18,
author = {Rob Stewart and
Kirsty Duncan and
Greg Michaelson and
Paulo Garcia and
Deepayan Bhowmik and
Andrew M. Wallace},
title = {{RIPL:} {A} Parallel Image Processing Language for FPGAs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {7:1--7:24},
year = {2018},
url = {https://doi.org/10.1145/3180481},
doi = {10.1145/3180481},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/StewartDMGBW18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/TatsumuraYB18,
author = {Kosuke Tatsumura and
Sadegh Yazdanshenas and
Vaughn Betz},
title = {Enhancing FPGAs with Magnetic Tunnel Junction-Based Block RAMs},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {6:1--6:22},
year = {2018},
url = {https://doi.org/10.1145/3154425},
doi = {10.1145/3154425},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/TatsumuraYB18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WijesunderaPSI18,
author = {Deshya Wijesundera and
Alok Prakash and
Thambipillai Srikanthan and
Achintha Ihalage},
title = {Framework for Rapid Performance Estimation of Embedded Soft Core Processors},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {2},
pages = {9:1--9:21},
year = {2018},
url = {https://doi.org/10.1145/3195801},
doi = {10.1145/3195801},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WijesunderaPSI18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/WongBR18,
author = {Henry Wong and
Vaughn Betz and
Jonathan Rose},
title = {High-Performance Instruction Scheduling Circuits for Superscalar Out-of-Order
Soft Processors},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {1:1--1:22},
year = {2018},
url = {https://doi.org/10.1145/3093741},
doi = {10.1145/3093741},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/WongBR18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/YuGHNQGWY18,
author = {Jincheng Yu and
Guangjun Ge and
Yiming Hu and
Xuefei Ning and
Jiantao Qiu and
Kaiyuan Guo and
Yu Wang and
Huazhong Yang},
title = {Instruction Driven Cross-layer {CNN} Accelerator for Fast Detection
on {FPGA}},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {3},
pages = {22:1--22:23},
year = {2018},
url = {https://doi.org/10.1145/3283452},
doi = {10.1145/3283452},
timestamp = {Sat, 08 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/trets/YuGHNQGWY18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/trets/ZhaoNALCD18,
author = {Zhuoran Zhao and
Nguyen T. H. Nguyen and
Dimitris Agiakatsikas and
Ganghee Lee and
Ediz Cetin and
Oliver Diessel},
title = {Fine-Grained Module-Based Error Recovery in FPGA-Based {TMR} Systems},
journal = {{ACM} Trans. Reconfigurable Technol. Syst.},
volume = {11},
number = {1},
pages = {4:1--4:23},
year = {2018},
url = {https://doi.org/10.1145/3173549},
doi = {10.1145/3173549},
timestamp = {Fri, 24 Apr 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/trets/ZhaoNALCD18.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
a service of 
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
retrieved on 2024-05-24 17:28 CEST from data curated by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
