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@article{DBLP:journals/todaes/AchterenCLD03,
  author       = {Tanja Van Achteren and
                  Francky Catthoor and
                  Rudy Lauwereins and
                  Geert Deconinck},
  title        = {Search space definition and exploration for nonuniform data reuse
                  opportunities in data-dominant applications},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {1},
  pages        = {125--139},
  year         = {2003},
  url          = {https://doi.org/10.1145/606603.606610},
  doi          = {10.1145/606603.606610},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/AchterenCLD03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/BlantonH03,
  author       = {Ronald D. Blanton and
                  John P. Hayes},
  title        = {On the properties of the input pattern fault model},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {1},
  pages        = {108--124},
  year         = {2003},
  url          = {https://doi.org/10.1145/606603.606609},
  doi          = {10.1145/606603.606609},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/BlantonH03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/ChangZWWW03,
  author       = {Yao{-}Wen Chang and
                  Kai Zhu and
                  Guang{-}Ming Wu and
                  D. F. Wong and
                  C. K. Wong},
  title        = {Analysis of {FPGA/FPIC} switch modules},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {1},
  pages        = {11--37},
  year         = {2003},
  url          = {https://doi.org/10.1145/606603.606605},
  doi          = {10.1145/606603.606605},
  timestamp    = {Sun, 02 Oct 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/ChangZWWW03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/ConstantinidesCL03,
  author       = {George A. Constantinides and
                  Peter Y. K. Cheung and
                  Wayne Luk},
  title        = {Synthesis of saturation arithmetic architectures},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {3},
  pages        = {334--354},
  year         = {2003},
  url          = {https://doi.org/10.1145/785411.785415},
  doi          = {10.1145/785411.785415},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/ConstantinidesCL03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/Edwards03,
  author       = {Stephen A. Edwards},
  title        = {Tutorial: Compiling concurrent languages for sequential processors},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {2},
  pages        = {141--187},
  year         = {2003},
  url          = {https://doi.org/10.1145/762488.762489},
  doi          = {10.1145/762488.762489},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/Edwards03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/El-MalehO03,
  author       = {Aiman H. El{-}Maleh and
                  Yahya E. Osais},
  title        = {Test vector decomposition-based static compaction algorithms for combinational
                  circuits},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {4},
  pages        = {430--459},
  year         = {2003},
  url          = {https://doi.org/10.1145/944027.944030},
  doi          = {10.1145/944027.944030},
  timestamp    = {Thu, 14 Oct 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/El-MalehO03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/GoelM03,
  author       = {Sandeep Kumar Goel and
                  Erik Jan Marinissen},
  title        = {{SOC} test architecture design for efficient utilization of test bandwidth},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {4},
  pages        = {399--429},
  year         = {2003},
  url          = {https://doi.org/10.1145/944027.944029},
  doi          = {10.1145/944027.944029},
  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/GoelM03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/JoneWLHC03,
  author       = {Wen{-}Ben Jone and
                  Jinn{-}Shyan Wang and
                  Hsueh{-}I Lu and
                  I. P. Hsu and
                  J.{-}Y. Chen},
  title        = {Design theory and implementation for low-power segmented bus systems},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {1},
  pages        = {38--54},
  year         = {2003},
  url          = {https://doi.org/10.1145/606603.606606},
  doi          = {10.1145/606603.606606},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/JoneWLHC03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/KimJKK03,
  author       = {Ki{-}Wook Kim and
                  Seong{-}Ook Jung and
                  Taewhan Kim and
                  Sung{-}Mo Kang},
  title        = {Minimum delay optimization for domino circuits - a coupling-aware
                  approach},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {2},
  pages        = {202--213},
  year         = {2003},
  url          = {https://doi.org/10.1145/762488.762491},
  doi          = {10.1145/762488.762491},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/KimJKK03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/Kuchcinski03,
  author       = {Krzysztof Kuchcinski},
  title        = {Constraints-driven scheduling and resource assignment},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {3},
  pages        = {355--383},
  year         = {2003},
  url          = {https://doi.org/10.1145/785411.785416},
  doi          = {10.1145/785411.785416},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/Kuchcinski03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/LeeLHT03,
  author       = {Chingren Lee and
                  Jenq Kuen Lee and
                  TingTing Hwang and
                  Shi{-}Chun Tsai},
  title        = {Compiler optimization on {VLIW} instruction scheduling for low power},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {2},
  pages        = {252--268},
  year         = {2003},
  url          = {https://doi.org/10.1145/762488.762494},
  doi          = {10.1145/762488.762494},
  timestamp    = {Sun, 22 Oct 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/LeeLHT03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/LeeP03,
  author       = {Jong{-}Yeol Lee and
                  In{-}Cheol Park},
  title        = {Address code generation for {DSP} instruction-set architectures},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {3},
  pages        = {384--395},
  year         = {2003},
  url          = {https://doi.org/10.1145/785411.785417},
  doi          = {10.1145/785411.785417},
  timestamp    = {Wed, 15 Jul 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/LeeP03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/LiCT03,
  author       = {Lei Li and
                  Krishnendu Chakrabarty and
                  Nur A. Touba},
  title        = {Test data compression using dictionaries with selective entries and
                  fixed-length indices},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {4},
  pages        = {470--490},
  year         = {2003},
  url          = {https://doi.org/10.1145/944027.944032},
  doi          = {10.1145/944027.944032},
  timestamp    = {Mon, 03 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/LiCT03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/LiLQSW03,
  author       = {Zhuo Li and
                  Xiang Lu and
                  Wangqi Qiu and
                  Weiping Shi and
                  D. M. H. Walker},
  title        = {A circuit level fault model for resistive bridges},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {4},
  pages        = {546--559},
  year         = {2003},
  url          = {https://doi.org/10.1145/944027.944036},
  doi          = {10.1145/944027.944036},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/LiLQSW03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/Lopez-VallejoL03,
  author       = {Marisa Luisa L{\'{o}}pez{-}Vallejo and
                  Juan Carlos L{\'{o}}pez},
  title        = {On the hardware-software partitioning problem: System modeling and
                  partitioning techniques},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {3},
  pages        = {269--297},
  year         = {2003},
  url          = {https://doi.org/10.1145/785411.785412},
  doi          = {10.1145/785411.785412},
  timestamp    = {Fri, 09 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/Lopez-VallejoL03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/NeubergerLCR03,
  author       = {Gustavo Neuberger and
                  Fernanda Gusm{\~{a}}o de Lima Kastensmidt and
                  Luigi Carro and
                  Ricardo Augusto da Luz Reis},
  title        = {A multiple bit upset tolerant {SRAM} memory},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {4},
  pages        = {577--590},
  year         = {2003},
  url          = {https://doi.org/10.1145/944027.944038},
  doi          = {10.1145/944027.944038},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/NeubergerLCR03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/NiggemeyerR03,
  author       = {Dirk Niggemeyer and
                  Elizabeth M. Rudnick},
  title        = {A data acquisition methodology for on-chip repair of embedded memories},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {4},
  pages        = {560--576},
  year         = {2003},
  url          = {https://doi.org/10.1145/944027.944037},
  doi          = {10.1145/944027.944037},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/NiggemeyerR03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/NummerS03,
  author       = {Muhammad Nummer and
                  Manoj Sachdev},
  title        = {Testing high-performance pipelined circuits with slow-speed testers},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {4},
  pages        = {506--521},
  year         = {2003},
  url          = {https://doi.org/10.1145/944027.944034},
  doi          = {10.1145/944027.944034},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/NummerS03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/ObenausS03,
  author       = {Stefan Thomas Obenaus and
                  Ted H. Szymanski},
  title        = {Gravity: Fast placement for 3-D {VLSI}},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {3},
  pages        = {298--315},
  year         = {2003},
  url          = {https://doi.org/10.1145/785411.785413},
  doi          = {10.1145/785411.785413},
  timestamp    = {Thu, 23 Jun 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/ObenausS03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/ParthasarathyKPJCG03,
  author       = {Kumar L. Parthasarathy and
                  Turker Kuyel and
                  Dana Price and
                  Le Jin and
                  Degang Chen and
                  Randall L. Geiger},
  title        = {{BIST} and production testing of ADCs using imprecise stimulus},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {4},
  pages        = {522--545},
  year         = {2003},
  url          = {https://doi.org/10.1145/944027.944035},
  doi          = {10.1145/944027.944035},
  timestamp    = {Tue, 26 Jul 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/todaes/ParthasarathyKPJCG03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/PinarL03,
  author       = {Ali Pinar and
                  C. L. Liu},
  title        = {Compacting sequences with invariant transition frequencies},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {2},
  pages        = {214--221},
  year         = {2003},
  url          = {https://doi.org/10.1145/762488.762492},
  doi          = {10.1145/762488.762492},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/PinarL03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/RawatW03,
  author       = {Shishpal Rawat and
                  Hans{-}Joachim Wunderlich},
  title        = {Introduction},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {4},
  pages        = {397--398},
  year         = {2003},
  url          = {https://doi.org/10.1145/944027.944028},
  doi          = {10.1145/944027.944028},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/RawatW03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/ReddyMKP03,
  author       = {Sudhakar M. Reddy and
                  Kohei Miyase and
                  Seiji Kajihara and
                  Irith Pomeranz},
  title        = {On test data volume reduction for multiple scan chain designs},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {4},
  pages        = {460--469},
  year         = {2003},
  url          = {https://doi.org/10.1145/944027.944031},
  doi          = {10.1145/944027.944031},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/ReddyMKP03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/RiepeS03,
  author       = {Michael A. Riepe and
                  Karem A. Sakallah},
  title        = {Transistor placement for noncomplementary digital {VLSI} cell synthesis},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {1},
  pages        = {81--107},
  year         = {2003},
  url          = {https://doi.org/10.1145/606603.606608},
  doi          = {10.1145/606603.606608},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/RiepeS03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/SinghSGS03,
  author       = {Adit D. Singh and
                  Markus Seuring and
                  Michael G{\"{o}}ssel and
                  Egor S. Sogomonyan},
  title        = {Multimode scan: Test per clock {BIST} for {IP} cores},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {4},
  pages        = {491--505},
  year         = {2003},
  url          = {https://doi.org/10.1145/944027.944033},
  doi          = {10.1145/944027.944033},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/SinghSGS03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/SinghalPAQB03,
  author       = {Vigyan Singhal and
                  Carl Pixley and
                  Adnan Aziz and
                  Shaz Qadeer and
                  Robert K. Brayton},
  title        = {Sequential optimization in the absence of global reset},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {2},
  pages        = {222--251},
  year         = {2003},
  url          = {https://doi.org/10.1145/762488.762493},
  doi          = {10.1145/762488.762493},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/SinghalPAQB03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/TragoudasD03,
  author       = {Spyros Tragoudas and
                  N. Denny},
  title        = {Path delay fault testing using test points},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {1},
  pages        = {1--10},
  year         = {2003},
  url          = {https://doi.org/10.1145/606603.606604},
  doi          = {10.1145/606603.606604},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/TragoudasD03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/WuCC03,
  author       = {Guang{-}Ming Wu and
                  Yun{-}Chih Chang and
                  Yao{-}Wen Chang},
  title        = {Rectilinear block placement using B\({}^{\mbox{*}}\)-trees},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {2},
  pages        = {188--202},
  year         = {2003},
  url          = {https://doi.org/10.1145/762488.762490},
  doi          = {10.1145/762488.762490},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/WuCC03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/YangWKGS03,
  author       = {Xiaojian Yang and
                  Maogang Wang and
                  Ryan Kastner and
                  Soheil Ghiasi and
                  Majid Sarrafzadeh},
  title        = {Congestion reduction during placement with provably good approximation
                  bound},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {3},
  pages        = {316--333},
  year         = {2003},
  url          = {https://doi.org/10.1145/785411.785414},
  doi          = {10.1145/785411.785414},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/YangWKGS03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/todaes/YaoCCG03,
  author       = {Bo Yao and
                  Hongyu Chen and
                  Chung{-}Kuan Cheng and
                  Ronald L. Graham},
  title        = {Floorplan representations: Complexity and connections},
  journal      = {{ACM} Trans. Design Autom. Electr. Syst.},
  volume       = {8},
  number       = {1},
  pages        = {55--80},
  year         = {2003},
  url          = {https://doi.org/10.1145/606603.606607},
  doi          = {10.1145/606603.606607},
  timestamp    = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/todaes/YaoCCG03.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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