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@article{DBLP:journals/todaes/AbouzeidCFRSS11,
author = {Fady Abouzeid and
Sylvain Clerc and
Fabian Firmin and
Marc Renaudin and
Tiempo Sas and
Gilles Sicard},
title = {40nm {CMOS} 0.35V-Optimized Standard Cell Libraries for Ultra-Low
Power Applications},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {35:1--35:17},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970369},
doi = {10.1145/1970353.1970369},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/AbouzeidCFRSS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/AinPDMMG11,
author = {Antara Ain and
Debjit Pal and
Pallab Dasgupta and
Siddhartha Mukhopadhyay and
Rajdeep Mukhopadhyay and
John Gough},
title = {Chassis: {A} Platform for Verifying {PMU} Integration Using Autogenerated
Behavioral Models},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {33:1--33:30},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970367},
doi = {10.1145/1970353.1970367},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/AinPDMMG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BernasconiC11,
author = {Anna Bernasconi and
Valentina Ciriani},
title = {Dimension-reducible Boolean functions based on affine spaces},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {2},
pages = {13:1--13:21},
year = {2011},
url = {https://doi.org/10.1145/1929943.1929945},
doi = {10.1145/1929943.1929945},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/BernasconiC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BondadeM11,
author = {Rajdeep Bondade and
Dongsheng Ma},
title = {Hardware-Software Codesign of an Embedded Multiple-Supply Power Management
Unit for Multicore SoCs Using an Adaptive Global/Local Power Allocation
and Processing Scheme},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {31:1--31:27},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970364},
doi = {10.1145/1970353.1970364},
timestamp = {Mon, 24 Aug 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/BondadeM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BruneelHS11,
author = {Karel Bruneel and
Wim Heirman and
Dirk Stroobandt},
title = {Dynamic data folding with parameterizable {FPGA} configurations},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {43:1--43:29},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003703},
doi = {10.1145/2003695.2003703},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/BruneelHS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/CauleyBHK11,
author = {Stephen Cauley and
Venkataramanan Balakrishnan and
Y. Charlie Hu and
Cheng{-}Kok Koh},
title = {A parallel branch-and-cut approach for detailed placement},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {2},
pages = {18:1--18:19},
year = {2011},
url = {https://doi.org/10.1145/1929943.1929950},
doi = {10.1145/1929943.1929950},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/CauleyBHK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ChatterjeeDB11,
author = {Debapriya Chatterjee and
Andrew DeOrio and
Valeria Bertacco},
title = {Gate-Level Simulation with {GPU} Computing},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {30:1--30:26},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970363},
doi = {10.1145/1970353.1970363},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/ChatterjeeDB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/CongJLZ11,
author = {Jason Cong and
Wei Jiang and
Bin Liu and
Yi Zou},
title = {Automatic memory partitioning and scheduling for throughput and power
optimization},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {2},
pages = {15:1--15:25},
year = {2011},
url = {https://doi.org/10.1145/1929943.1929947},
doi = {10.1145/1929943.1929947},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/CongJLZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/DongL11,
author = {Wei Dong and
Peng Li},
title = {Parallel circuit simulation with adaptively controlled projective
integration},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {44:1--44:24},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003704},
doi = {10.1145/2003695.2003704},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/DongL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/DopicoPRG11,
author = {Antonio Garc{\'{\i}}a Dopico and
Antonio P{\'{e}}rez and
Santiago Rodr{\'{\i}}guez and
Maria Isabel Garc{\'{\i}}a},
title = {A New Algorithm for {VHDL} Parallel Simulation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {27:1--27:31},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970360},
doi = {10.1145/1970353.1970360},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/DopicoPRG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/DuarteHZSHG11,
author = {Filipa Duarte and
Jos Hulzink and
Jun Zhou and
Jan Stuijt and
Jos Huisken and
Harmke de Groot},
title = {A 36{\(\mu\)}W heartbeat-detection processor for a wireless sensor
node},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {51:1--51:19},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003711},
doi = {10.1145/2003695.2003711},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/DuarteHZSHG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/FournierZKS11,
author = {Laurent Fournier and
Avi Ziv and
Ekaterina Kutsy and
Ofer Strichman},
title = {A probabilistic analysis of coverage methods},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {38:1--38:20},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003698},
doi = {10.1145/2003695.2003698},
timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/FournierZKS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/HanCRK11,
author = {Yiding Han and
Koushik Chakraborty and
Sanghamitra Roy and
Vilasita Kuntamukkala},
title = {Design and Implementation of a Throughput-Optimized {GPU} Floorplanning
Algorithm},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {23:1--23:21},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970356},
doi = {10.1145/1970353.1970356},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/HanCRK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/HealyMLL11,
author = {Michael B. Healy and
Fayez Mohamood and
Hsien{-}Hsin S. Lee and
Sung Kyu Lim},
title = {Integrated microarchitectural floorplanning and run-time controller
for inductive noise mitigation},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {46:1--46:25},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003706},
doi = {10.1145/2003695.2003706},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/HealyMLL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/HsuPB11,
author = {Chia{-}Jui Hsu and
Jos{\'{e}} Luis Pino and
Shuvra S. Bhattacharyya},
title = {Multithreaded Simulation for Synchronous Dataflow Graphs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {25:1--25:23},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970358},
doi = {10.1145/1970353.1970358},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/HsuPB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KeutzerLSZ11,
author = {Kurt Keutzer and
Peng Li and
Li Shang and
Hai Zhou},
title = {A Special Section on Multicore Parallel {CAD:} Algorithm Design and
Programming},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {21:1--21:2},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970354},
doi = {10.1145/1970353.1970354},
timestamp = {Wed, 16 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/KeutzerLSZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KimK11,
author = {Tak{-}Yung Kim and
Taewhan Kim},
title = {Clock Tree synthesis for TSV-based 3D {IC} designs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {48:1--48:21},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003708},
doi = {10.1145/2003695.2003708},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/KimK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KimLSP11,
author = {Yongjoo Kim and
Jongeun Lee and
Aviral Shrivastava and
Yunheung Paek},
title = {Memory access optimization in compilation for coarse-grained reconfigurable
architectures},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {42:1--42:27},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003702},
doi = {10.1145/2003695.2003702},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/KimLSP11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiCC11,
author = {Yih{-}Lang Li and
Yu{-}Ning Chang and
Wen{-}Nai Cheng},
title = {A gridless routing system with nonslicing floorplanning-based crosstalk
reduction on gridless track assignment},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {2},
pages = {19:1--19:25},
year = {2011},
url = {https://doi.org/10.1145/1929943.1929951},
doi = {10.1145/1929943.1929951},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LiCC11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiaoS11,
author = {Xiongfei Liao and
Thambipillai Srikanthan},
title = {Accelerating UNISIM-Based Cycle-Level Microarchitectural Simulations
on Multicore Platforms},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {26:1--26:25},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970359},
doi = {10.1145/1970353.1970359},
timestamp = {Wed, 14 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LiaoS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiuH11,
author = {Yifang Liu and
Jiang Hu},
title = {GPU-Based Parallelization for Fast Circuit Optimization},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {24:1--24:14},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970357},
doi = {10.1145/1970353.1970357},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LiuH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LiuWK11,
author = {Yu Liu and
Kaijie Wu and
Ramesh Karri},
title = {Scan-based attacks on linear feedback shift register based stream
ciphers},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {2},
pages = {20:1--20:15},
year = {2011},
url = {https://doi.org/10.1145/1929943.1929952},
doi = {10.1145/1929943.1929952},
timestamp = {Sun, 22 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/LiuWK11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LuT11,
author = {Jianchao Lu and
Baris Taskin},
title = {Clock buffer polarity assignment with skew tuning},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {49:1--49:22},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003709},
doi = {10.1145/2003695.2003709},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LuT11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/LudwinB11,
author = {Adrian Ludwin and
Vaughn Betz},
title = {Efficient and Deterministic Parallel Placement for FPGAs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {22:1--22:23},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970355},
doi = {10.1145/1970353.1970355},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/LudwinB11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/MaestroRBWW11,
author = {Juan Antonio Maestro and
Pedro Reviriego and
Sanghyeon Baeg and
Shi{-}Jie Wen and
Richard Wong},
title = {Mitigating the effects of large multiple cell upsets (MCUs) in memories},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {45:1--45:10},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003705},
doi = {10.1145/2003695.2003705},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/MaestroRBWW11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/MittalJM11,
author = {Kartikey Mittal and
Arpit Joshi and
Madhu Mutyam},
title = {Timing variation-aware scheduling and resource binding in high-level
synthesis},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {40:1--40:19},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003700},
doi = {10.1145/2003695.2003700},
timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/MittalJM11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Pedram11,
author = {Massoud Pedram},
title = {Call for papers: Verification issue and challenges with multicore
systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {2},
pages = {12:1},
year = {2011},
url = {https://doi.org/10.1145/1929943.1929944},
doi = {10.1145/1929943.1929944},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Pedram11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/PomeranzR11,
author = {Irith Pomeranz and
Sudhakar M. Reddy},
title = {Reducing the switching activity of test sequences under transparent-scan},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {2},
pages = {17:1--17:21},
year = {2011},
url = {https://doi.org/10.1145/1929943.1929949},
doi = {10.1145/1929943.1929949},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/PomeranzR11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/QiuS11,
author = {Meikang Qiu and
Edwin Hsing{-}Mean Sha},
title = {2011 {ACM} {TODAES} best paper award},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {36:1},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003696},
doi = {10.1145/2003695.2003696},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/QiuS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Sen11,
author = {Alper Sen},
title = {Concurrency-oriented verification and coverage of system-level designs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {37:1--37:25},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003697},
doi = {10.1145/2003695.2003697},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/Sen11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/StittV11,
author = {Greg Stitt and
Frank Vahid},
title = {Thread Warping: Dynamic and Transparent Synthesis of Thread Accelerators},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {32:1--32:21},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970365},
doi = {10.1145/1970353.1970365},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/StittV11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SunS11,
author = {Wei{-}Tsun Sun and
Zoran Salcic},
title = {GALS-Designer: {A} design framework for {GALS} software systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {39:1--39:24},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003699},
doi = {10.1145/2003695.2003699},
timestamp = {Sat, 24 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/SunS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/WangG11,
author = {Xiaofang (Maggie) Wang and
Pallav Gupta},
title = {Resource-constrained multiprocessor synthesis for floating-point applications
on FPGAs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {41:1--41:29},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003701},
doi = {10.1145/2003695.2003701},
timestamp = {Sat, 09 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/WangG11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/WangJYZ11,
author = {Shaoxi Wang and
Xinzhang Jia and
Arthur B. Yeh and
Lihong Zhang},
title = {Analog layout retargeting using geometric programming},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {50:1--50:11},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003710},
doi = {10.1145/2003695.2003710},
timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/WangJYZ11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/WangLLQSS11,
author = {Yi Wang and
Hui Liu and
Duo Liu and
Zhiwei Qin and
Zili Shao and
Edwin Hsing{-}Mean Sha},
title = {Overhead-aware energy optimization for real-time streaming applications
on multiprocessor System-on-Chip},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {2},
pages = {14:1--14:32},
year = {2011},
url = {https://doi.org/10.1145/1929943.1929946},
doi = {10.1145/1929943.1929946},
timestamp = {Fri, 10 Nov 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/WangLLQSS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/Yan11,
author = {Jin{-}Tai Yan},
title = {{IO} connection assignment and {RDL} routing for flip-chip designs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {4},
pages = {47:1--47:20},
year = {2011},
url = {https://doi.org/10.1145/2003695.2003707},
doi = {10.1145/2003695.2003707},
timestamp = {Sat, 09 Apr 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/Yan11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/YanHLLL11,
author = {Guihai Yan and
Yinhe Han and
Hui Liu and
Xiaoyao Liang and
Xiaowei Li},
title = {MicroFix: Using timing interpolation and delay sensors for power reduction},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {2},
pages = {16:1--16:21},
year = {2011},
url = {https://doi.org/10.1145/1929943.1929948},
doi = {10.1145/1929943.1929948},
timestamp = {Tue, 23 May 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/YanHLLL11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/YuRH11,
author = {Yue Yu and
Shangping Ren and
Xiaobo Sharon Hu},
title = {A Metric for Quantifying Similarity between Timing Constraint Sets
in Real-Time Systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {34:1--34:33},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970368},
doi = {10.1145/1970353.1970368},
timestamp = {Sat, 07 Sep 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/YuRH11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ZengFLS11,
author = {Zhiyu Zeng and
Zhuo Feng and
Peng Li and
Vivek Sarin},
title = {Locality-Driven Parallel Static Analysis for Power Delivery Networks},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {28:1--28:17},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970361},
doi = {10.1145/1970353.1970361},
timestamp = {Thu, 24 Oct 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/ZengFLS11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ZhuWD11,
author = {Yuhao Zhu and
Bo D. Wang and
Yangdong Deng},
title = {Massively Parallel Logic Simulation with GPUs},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {3},
pages = {29:1--29:20},
year = {2011},
url = {https://doi.org/10.1145/1970353.1970362},
doi = {10.1145/1970353.1970362},
timestamp = {Tue, 23 Jul 2019 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/ZhuWD11.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/BolFL10,
author = {David Bol and
Denis Flandre and
Jean{-}Didier Legat},
title = {Nanometer {MOSFET} Effects on the Minimum-Energy Point of Sub-45nm
Subthreshold Logic - Mitigation at Technology and Circuit Levels},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {1},
pages = {2:1--2:26},
year = {2010},
url = {https://doi.org/10.1145/1870109.1870111},
doi = {10.1145/1870109.1870111},
timestamp = {Fri, 09 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/BolFL10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/CalimeraMP10,
author = {Andrea Calimera and
Enrico Macii and
Massimo Poncino},
title = {NBTI-Aware Clustered Power Gating},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {1},
pages = {3:1--3:25},
year = {2010},
url = {https://doi.org/10.1145/1870109.1870112},
doi = {10.1145/1870109.1870112},
timestamp = {Wed, 14 Jun 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/CalimeraMP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ChangH10a,
author = {Naehyuck Chang and
J{\"{o}}rg Henkel},
title = {Guest Editorial: Current Trends in Low-Power Design},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {1},
pages = {1:1--1:8},
year = {2010},
url = {https://doi.org/10.1145/1870109.1870110},
doi = {10.1145/1870109.1870110},
timestamp = {Sun, 28 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/ChangH10a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/CongLMZ10,
author = {Jason Cong and
Bin Liu and
Rupak Majumdar and
Zhiru Zhang},
title = {Behavior-Level Observability Analysis for Operation Gating in Low-Power
Behavioral Synthesis},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {1},
pages = {4:1--4:29},
year = {2010},
url = {https://doi.org/10.1145/1870109.1870113},
doi = {10.1145/1870109.1870113},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/todaes/CongLMZ10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/DhimanMR10,
author = {Gaurav Dhiman and
Giacomo Marchetti and
Tajana Rosing},
title = {vGreen: {A} System for Energy-Efficient Management of Virtual Machines},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {1},
pages = {6:1--6:27},
year = {2010},
url = {https://doi.org/10.1145/1870109.1870115},
doi = {10.1145/1870109.1870115},
timestamp = {Sun, 28 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/DhimanMR10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/JayakumarK10,
author = {Nikhil Jayakumar and
Sunil P. Khatri},
title = {A Simultaneous Input Vector Control and Circuit Modification Technique
to Reduce Leakage with Zero Delay Penalty},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {1},
pages = {9:1--9:20},
year = {2010},
url = {https://doi.org/10.1145/1870109.1870118},
doi = {10.1145/1870109.1870118},
timestamp = {Sun, 28 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/JayakumarK10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/KimC10,
author = {Jinsik Kim and
Pai H. Chou},
title = {Energy-Efficient Progressive Remote Update for Flash-Based Firmware
of Networked Embedded Systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {1},
pages = {7:1--7:26},
year = {2010},
url = {https://doi.org/10.1145/1870109.1870116},
doi = {10.1145/1870109.1870116},
timestamp = {Sun, 28 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/KimC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/SinghN10,
author = {Montek Singh and
Steven M. Nowick},
title = {{ACM} Journal on Emerging Technologies in Computing Systems},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {1},
pages = {11:1},
year = {2010},
url = {https://doi.org/10.1145/1870109.1870120},
doi = {10.1145/1870109.1870120},
timestamp = {Sun, 28 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/SinghN10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/ThorolfssonMDF10,
author = {Thorlindur Thorolfsson and
Samson Melamed and
W. Rhett Davis and
Paul D. Franzon},
title = {Low-Power Hypercube Divided Memory {FFT} Engine Using 3D Integration},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {1},
pages = {5:1--5:25},
year = {2010},
url = {https://doi.org/10.1145/1870109.1870114},
doi = {10.1145/1870109.1870114},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/ThorolfssonMDF10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/WuC10,
author = {Yu{-}Ze Wu and
Mango Chia{-}Tso Chao},
title = {Scan-Cell Reordering for Minimizing Scan-Shift Power Based on Nonspecified
Test Cubes},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {1},
pages = {10:1--10:29},
year = {2010},
url = {https://doi.org/10.1145/1870109.1870119},
doi = {10.1145/1870109.1870119},
timestamp = {Sun, 28 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/WuC10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/todaes/YuP10,
author = {Chenjie Yu and
Peter Petrov},
title = {Energy- and Performance-Efficient Communication Framework for Embedded
MPSoCs through Application-Driven Release Consistency},
journal = {{ACM} Trans. Design Autom. Electr. Syst.},
volume = {16},
number = {1},
pages = {8:1--8:39},
year = {2010},
url = {https://doi.org/10.1145/1870109.1870117},
doi = {10.1145/1870109.1870117},
timestamp = {Sun, 28 May 2017 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/todaes/YuP10.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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