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@article{DBLP:journals/tcad/0002W12,
author = {Qiang Ma and
Martin D. F. Wong},
title = {NP-Completeness and an Approximation Algorithm for Rectangle Escape
Problem With Application to {PCB} Routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1356--1365},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2193581},
doi = {10.1109/TCAD.2012.2193581},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/0002W12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AdirNZ12,
author = {Allon Adir and
Amir Nahir and
Avi Ziv},
title = {Concurrent Generation of Concurrent Programs for Post-Silicon Validation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1297--1302},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2189394},
doi = {10.1109/TCAD.2012.2189394},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AdirNZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AgyekumN12,
author = {Melinda Y. Agyekum and
Steven M. Nowick},
title = {Error-Correcting Unordered Codes and Hardware Support for Robust Asynchronous
Global Communication},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {75--88},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2165070},
doi = {10.1109/TCAD.2011.2165070},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AgyekumN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AlpaslanKMHD12,
author = {Elif Alpaslan and
Bram Kruseman and
Ananta K. Majhi and
Wilmar M. Heuvelman and
Jennifer Dworak},
title = {{NIM-X:} {A} Noise Index Model-Based X-Filling Technique to Overcome
the Power Supply Switching Noise Effects on Path Delay Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {809--813},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2179040},
doi = {10.1109/TCAD.2011.2179040},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AlpaslanKMHD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/AnsaloniTPD12,
author = {Giovanni Ansaloni and
Kazuyuki Tanimura and
Laura Pozzi and
Nikil D. Dutt},
title = {Integrated Kernel Partitioning and Scheduling for Coarse-Grained Reconfigurable
Arrays},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1803--1816},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2209886},
doi = {10.1109/TCAD.2012.2209886},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/AnsaloniTPD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BadamiK12,
author = {Komail M. H. Badami and
Shreepad Karmalkar},
title = {Quasi-Static Compact Model for Coupling Between Aligned Contacts on
Finite Substrates With Insulating or Conducting Backplanes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {858--867},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2184106},
doi = {10.1109/TCAD.2012.2184106},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BadamiK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Banerjee12,
author = {Ansuman Banerjee},
title = {Verifying Coalitions in 3-Party Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1439--1451},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2194491},
doi = {10.1109/TCAD.2012.2194491},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Banerjee12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BarrioHMMM12,
author = {Alberto A. Del Barrio and
Rom{\'{a}}n Hermida and
Seda Ogrenci Memik and
Jos{\'{e}} M. Mend{\'{\i}}as and
Mar{\'{\i}}a C. Molina},
title = {Multispeculative Addition Applied to Datapath Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1817--1830},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2208966},
doi = {10.1109/TCAD.2012.2208966},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BarrioHMMM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/BrambillaGG12,
author = {Angelo Brambilla and
Giambattista Gruosso and
Giancarlo Storti Gajani},
title = {{MTFS:} Mixed Time-Frequency Method for the Steady-State Analysis
of Almost-Periodic Nonlinear Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1346--1355},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2191553},
doi = {10.1109/TCAD.2012.2191553},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/BrambillaGG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChangJC12,
author = {Hua{-}Yu Chang and
Iris Hui{-}Ru Jiang and
Yao{-}Wen Chang},
title = {Timing {ECO} Optimization Via B{\'{e}}zier Curve Smoothing and
Fixability Identification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1857--1866},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2209117},
doi = {10.1109/TCAD.2012.2209117},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChangJC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenLT12,
author = {Ting{-}Ju Chen and
Jin{-}Fu Li and
Tsu{-}Wei Tseng},
title = {Cost-Efficient Built-In Redundancy Analysis With Optimal Repair Rate
for RAMs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {930--940},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2181510},
doi = {10.1109/TCAD.2011.2181510},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenLT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenO12,
author = {Mingjing Chen and
Alex Orailoglu},
title = {On Diagnosis of Timing Failures in Scan Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1102--1115},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2186298},
doi = {10.1109/TCAD.2012.2186298},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenW12,
author = {Yung{-}Chih Chen and
Chun{-}Yao Wang},
title = {Logic Restructuring Using Node Addition and Removal},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {260--270},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2167327},
doi = {10.1109/TCAD.2011.2167327},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenWC12,
author = {Quan Chen and
Shih{-}Hung Weng and
Chung{-}Kuan Cheng},
title = {A Practical Regularization Technique for Modified Nodal Analysis in
Large-Scale Time-Domain Circuit Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1031--1040},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2184761},
doi = {10.1109/TCAD.2012.2184761},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenWC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChenZ12,
author = {Jianli Chen and
Wenxing Zhu},
title = {An Analytical Placer for {VLSI} Standard Cell Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1208--1221},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2190289},
doi = {10.1109/TCAD.2012.2190289},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChenZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChoLM12,
author = {Hyungmin Cho and
Larkhoon Leem and
Subhasish Mitra},
title = {{ERSA:} Error Resilient System Architecture for Probabilistic Applications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {546--558},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2179038},
doi = {10.1109/TCAD.2011.2179038},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChoLM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChocklerKP12,
author = {Hana Chockler and
Daniel Kroening and
Mitra Purandare},
title = {Computing Mutation Coverage in Interpolation-Based Model Checking},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {765--778},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2180382},
doi = {10.1109/TCAD.2011.2180382},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChocklerKP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChouhanBB12,
author = {Sonali Chouhan and
M. Balakrishnan and
Ranjan Bose},
title = {System-Level Design Space Exploration Methodology for Energy-Efficient
Sensor Node Configurations: An Experimental Validation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {586--596},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2176729},
doi = {10.1109/TCAD.2011.2176729},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChouhanBB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChungA12,
author = {Jaeyong Chung and
Jacob A. Abraham},
title = {Refactoring of Timing Graphs and Its Use in Capturing Topological
Correlation in {SSTA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {485--496},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2176731},
doi = {10.1109/TCAD.2011.2176731},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChungA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChungA12a,
author = {Jaeyong Chung and
Jacob A. Abraham},
title = {On Computing Criticality in Refactored Timing Graphs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1935--1939},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2213819},
doi = {10.1109/TCAD.2012.2213819},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ChungA12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChungXZA12,
author = {Jaeyong Chung and
Jinjun Xiong and
Vladimir Zolotov and
Jacob A. Abraham},
title = {Path Criticality Computation in Parameterized Statistical Timing Analysis
Using a Novel Operator},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {497--508},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2179042},
doi = {10.1109/TCAD.2011.2179042},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChungXZA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ChungXZA12a,
author = {Jaeyong Chung and
Jinjun Xiong and
Vladimir Zolotov and
Jacob A. Abraham},
title = {Testability-Driven Statistical Path Selection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1275--1287},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2190067},
doi = {10.1109/TCAD.2012.2190067},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ChungXZA12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ConstantinKSCZ12,
author = {Nicolas G. Constantin and
Kai H. Kwok and
Hongxiao Shao and
Cristian Cismaru and
Peter J. Zampardi},
title = {Formulations and a Computer-Aided Test Method for the Estimation of
{IMD} Levels in an Envelope Feedback {RFIC} Power Amplifier},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1881--1893},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2207954},
doi = {10.1109/TCAD.2012.2207954},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ConstantinKSCZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/CuiM12,
author = {Jin Cui and
Douglas L. Maskell},
title = {A Fast High-Level Event-Driven Thermal Estimator for Dynamic Thermal
Aware Scheduling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {904--917},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2183371},
doi = {10.1109/TCAD.2012.2183371},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/CuiM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DaneshtalabELPT12,
author = {Masoud Daneshtalab and
Masoumeh Ebrahimi and
Pasi Liljeberg and
Juha Plosila and
Hannu Tenhunen},
title = {Memory-Efficient On-Chip Network With Adaptive Interfaces},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {146--159},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2160348},
doi = {10.1109/TCAD.2011.2160348},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DaneshtalabELPT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DasBD12,
author = {Sourasis Das and
Ansuman Banerjee and
Pallab Dasgupta},
title = {Early Analysis of Critical Faults: An Approach to Test Generation
From Formal Specifications},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {447--451},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2171183},
doi = {10.1109/TCAD.2011.2171183},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DasBD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DeOrioFBSBHC12,
author = {Andrew DeOrio and
David Fick and
Valeria Bertacco and
Dennis Sylvester and
David T. Blaauw and
Jin Hu and
Gregory K. Chen},
title = {A Reliable Routing Architecture and Algorithm for NoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {726--739},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2181509},
doi = {10.1109/TCAD.2011.2181509},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DeOrioFBSBHC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/DongXXJ12,
author = {Xiangyu Dong and
Cong Xu and
Yuan Xie and
Norman P. Jouppi},
title = {NVSim: {A} Circuit-Level Performance, Energy, and Area Model for Emerging
Nonvolatile Memory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {994--1007},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2185930},
doi = {10.1109/TCAD.2012.2185930},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/DongXXJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EickG12,
author = {Michael Eick and
Helmut E. Graeb},
title = {{MARS:} Matching-Driven Analog Sizing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1145--1158},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2190069},
doi = {10.1109/TCAD.2012.2190069},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EickG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/EjlaliAE12,
author = {Alireza Ejlali and
Bashir M. Al{-}Hashimi and
Petru Eles},
title = {Low-Energy Standby-Sparing for Hard Real-Time Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {329--342},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2173488},
doi = {10.1109/TCAD.2011.2173488},
timestamp = {Thu, 23 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/EjlaliAE12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FangCC12,
author = {Shao{-}Yun Fang and
Szu{-}Yu Chen and
Yao{-}Wen Chang},
title = {Native-Conflict and Stitch-Aware Wire Perturbation for Double Patterning
Technology},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {703--716},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2179039},
doi = {10.1109/TCAD.2011.2179039},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FangCC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FangCWG12,
author = {Hongxia Fang and
Krishnendu Chakrabarty and
Zhiyuan Wang and
Xinli Gu},
title = {Reproduction and Detection of Board-Level Functional Failure},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {630--643},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2175391},
doi = {10.1109/TCAD.2011.2175391},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/FangCWG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FangCWG12a,
author = {Hongxia Fang and
Krishnendu Chakrabarty and
Zhiyuan Wang and
Xinli Gu},
title = {Diagnosis of Board-Level Functional Failures Under Uncertainty Using
Dempster-Shafer Theory},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1586--1599},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2198884},
doi = {10.1109/TCAD.2012.2198884},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/FangCWG12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FennibayY012,
author = {Dogan Fennibay and
Arda Yurdakul and
Alper Sen},
title = {A Heterogeneous Simulation and Modeling Framework for Automation Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1642--1655},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2199116},
doi = {10.1109/TCAD.2012.2199116},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FennibayY012.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/FiliolOM12,
author = {Hubert Filiol and
Ian O'Connor and
Dominique Morche},
title = {Analog {IC} Variability Bound Estimation Using the Cornish-Fisher
Expansion},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1457--1461},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2191552},
doi = {10.1109/TCAD.2012.2191552},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/FiliolOM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ForemanHCV12,
author = {Eric A. Foreman and
Peter A. Habitz and
Ming{-}C. Cheng and
Chandu Visweswariah},
title = {A Novel Method for Reducing Metal Variation With Statistical Static
Timing Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1293--1297},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2190068},
doi = {10.1109/TCAD.2012.2190068},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ForemanHCV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GaoYWY12,
author = {Mingzhi Gao and
Zuochang Ye and
Yan Wang and
Zhiping Yu},
title = {Efficient Full-Chip Statistical Leakage Analysis Based on Fast Matrix
Vector Product},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {356--369},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2171962},
doi = {10.1109/TCAD.2011.2171962},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GaoYWY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhaidaG12,
author = {Rani S. Ghaida and
Puneet Gupta},
title = {{DRE:} {A} Framework for Early Co-Evaluation of Design Rules, Technology
Choices, and Layout Methodologies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1379--1392},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2192477},
doi = {10.1109/TCAD.2012.2192477},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhaidaG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GhoshMPCM12,
author = {Jyotirmoy Ghosh and
Siddhartha Mukhopadhyay and
Amit Patra and
Barry Culpepper and
Tawen Mei},
title = {Estimation of dc Performance of a Lateral Power {MOSFET} Using Distributed
Cell Model},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1452--1456},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2193578},
doi = {10.1109/TCAD.2012.2193578},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GhoshMPCM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GladigauHT12,
author = {Jens Gladigau and
Christian Haubelt and
J{\"{u}}rgen Teich},
title = {Model-Based Virtual Prototype Acceleration},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1572--1585},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2205148},
doi = {10.1109/TCAD.2012.2205148},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/GladigauHT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/GortA12,
author = {Marcel Gort and
Jason Helge Anderson},
title = {Accelerating {FPGA} Routing Through Parallelization and Engineering
Enhancements Special Section on {PAR-CAD} 2010},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {61--74},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2165715},
doi = {10.1109/TCAD.2011.2165715},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/GortA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Hajj12,
author = {Ibrahim N. Hajj},
title = {Extended Nodal Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {89--100},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2167330},
doi = {10.1109/TCAD.2011.2167330},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Hajj12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HarutyunyanSVZ12,
author = {Gurgen Harutyunyan and
Samvel K. Shoukourian and
Valery A. Vardanian and
Yervant Zorian},
title = {A New Method for March Test Algorithm Generation and Its Application
for Fault Detection in RAMs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {941--949},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2184107},
doi = {10.1109/TCAD.2012.2184107},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HarutyunyanSVZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HeloueON12,
author = {Khaled R. Heloue and
Sari Onaissi and
Farid N. Najm},
title = {Efficient Block-Based Parameterized Timing Analysis Covering All Potentially
Critical Paths},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {472--484},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2175392},
doi = {10.1109/TCAD.2011.2175392},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HeloueON12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HernandezRSFD12,
author = {Carles Hern{\'{a}}ndez and
Antoni Roca and
Federico Silla and
Jos{\'{e}} Flich and
Jos{\'{e}} Duato},
title = {On the Impact of Within-Die Process Variation in GALS-Based NoC Performance},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {294--307},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2170071},
doi = {10.1109/TCAD.2011.2170071},
timestamp = {Mon, 18 Dec 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HernandezRSFD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HoJC12,
author = {Kuan{-}Hsien Ho and
Jie{-}Hong Roland Jiang and
Yao{-}Wen Chang},
title = {{TRECO:} Dynamic Technology Remapping for Timing Engineering Change
Orders},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1723--1733},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2201480},
doi = {10.1109/TCAD.2012.2201480},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HoJC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Hong12,
author = {Hao{-}Chiao Hong},
title = {A Static Linear Behavior Analog Fault Model for Switched-Capacitor
Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {597--609},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2173492},
doi = {10.1109/TCAD.2011.2173492},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Hong12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsiehHC12,
author = {Yi{-}Ling Hsieh and
Tsung{-}Yi Ho and
Krishnendu Chakrabarty},
title = {A Reagent-Saving Mixing Algorithm for Preparing Multiple-Target Biochemical
Samples Using Digital Microfluidics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1656--1669},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2202396},
doi = {10.1109/TCAD.2012.2202396},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/HsiehHC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsuC12,
author = {Meng{-}Kai Hsu and
Yao{-}Wen Chang},
title = {Unified Analytical Global Placement for Large-Scale Mixed-Size Circuit
Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1366--1378},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2193582},
doi = {10.1109/TCAD.2012.2193582},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsuC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HsuSPH12,
author = {Kai{-}Ti Hsu and
Subarna Sinha and
Yu{-}Chuan Pi and
Tsung{-}Yi Ho},
title = {A Hierarchy-Based Distributed Algorithm for Layout Geometry Operations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1546--1557},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2201155},
doi = {10.1109/TCAD.2012.2201155},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HsuSPH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuK12,
author = {Jiang Hu and
Cheng{-}Kok Koh},
title = {Guest Editorial Special Section on the 2011 International Symposium
on Physical Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {165--166},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2181741},
doi = {10.1109/TCAD.2011.2181741},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/HuangL12,
author = {Yu{-}Jen Huang and
Jin{-}Fu Li},
title = {Built-In Self-Repair Scheme for the TSVs in 3-D ICs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1600--1613},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2198475},
doi = {10.1109/TCAD.2012.2198475},
timestamp = {Tue, 17 Oct 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/HuangL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/IbrahimBB12,
author = {Walid Ibrahim and
Valeriu Beiu and
Azam Beg},
title = {{GREDA:} {A} Fast and More Accurate Gate Reliability {EDA} Tool},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {509--521},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2176123},
doi = {10.1109/TCAD.2011.2176123},
timestamp = {Fri, 09 Apr 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/IbrahimBB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JanickiKMMRT12,
author = {Jakub Janicki and
Mark Kassab and
Grzegorz Mrugalski and
Nilanjan Mukherjee and
Janusz Rajski and
Jerzy Tyszer},
title = {{EDT} Bandwidth Management in SoC Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1894--1907},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2205385},
doi = {10.1109/TCAD.2012.2205385},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JanickiKMMRT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangC12,
author = {Yao{-}Lin Jiang and
Hai{-}Bao Chen},
title = {Application of General Orthogonal Polynomials to Fast Simulation of
Nonlinear Descriptor Systems Through Piecewise-Linear Approximation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {804--808},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2179879},
doi = {10.1109/TCAD.2011.2179879},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JiangCY12,
author = {Iris Hui{-}Ru Jiang and
Chih{-}Long Chang and
Yu{-}Ming Yang},
title = {{INTEGRA:} Fast Multibit Flip-Flop Clustering for Clock Power Saving},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {192--204},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2177459},
doi = {10.1109/TCAD.2011.2177459},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JiangCY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JinG12,
author = {Xin Jin and
Satoshi Goto},
title = {Hilbert Transform-Based Workload Prediction and Dynamic Frequency
Scaling for Power-Efficient Video Encoding},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {649--661},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2180383},
doi = {10.1109/TCAD.2011.2180383},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JinG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JungK12,
author = {Jongyoon Jung and
Taewhan Kim},
title = {Variation-Aware False Path Analysis Based on Statistical Dynamic Timing
Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1684--1697},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2202392},
doi = {10.1109/TCAD.2012.2202392},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JungK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/JungMPL12,
author = {Moongon Jung and
Joydeep Mitra and
David Z. Pan and
Sung Kyu Lim},
title = {{TSV} Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization
for 3-D {IC}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1194--1207},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2188400},
doi = {10.1109/TCAD.2012.2188400},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/JungMPL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KagalwallaGPM12,
author = {Abde Ali Kagalwalla and
Puneet Gupta and
Christopher J. Progler and
Steve McDonald},
title = {Design-Aware Mask Inspection},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {690--702},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2181909},
doi = {10.1109/TCAD.2011.2181909},
timestamp = {Thu, 28 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KagalwallaGPM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KahngKKS12,
author = {Andrew B. Kahng and
Seokhyeong Kang and
Rakesh Kumar and
John Sartori},
title = {Recovery-Driven Design: Exploiting Error Resilience in Design of Energy-Efficient
Processors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {404--417},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2172610},
doi = {10.1109/TCAD.2011.2172610},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KahngKKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KakoulliST12,
author = {Elena Kakoulli and
Vassos Soteriou and
Theocharis Theocharides},
title = {Intelligent Hotspot Prediction for Network-on-Chip-Based Multicore
Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {418--431},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2170568},
doi = {10.1109/TCAD.2011.2170568},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KakoulliST12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KapreD12,
author = {Nachiket Kapre and
Andr{\'{e}} DeHon},
title = {{\textdollar}\{{\textbackslash}rm SPICE\}2{\textdollar}: Spatial Processors
Interconnected for Concurrent Execution for Accelerating the {SPICE}
Circuit Simulator Using an {FPGA}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {9--22},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2173199},
doi = {10.1109/TCAD.2011.2173199},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KapreD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KavousianosCJP12,
author = {Xrysovalantis Kavousianos and
Krishnendu Chakrabarty and
Arvind Jain and
Rubin A. Parekhji},
title = {Test Schedule Optimization for Multicore SoCs: Handling Dynamic Voltage
Scaling and Multiple Voltage Islands},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1754--1766},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2203600},
doi = {10.1109/TCAD.2012.2203600},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KavousianosCJP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KazmierskiWAM12,
author = {Tom J. Kazmierski and
Leran Wang and
Bashir M. Al{-}Hashimi and
Geoff V. Merrett},
title = {An Explicit Linearized State-Space Technique for Accelerated Simulation
of Electromagnetic Vibration Energy Harvesters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {522--531},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2176124},
doi = {10.1109/TCAD.2011.2176124},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KazmierskiWAM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimKE12,
author = {Dongchul Kim and
Hyewon Kim and
Yungseon Eo},
title = {Analytical Eye-Diagram Determination for the Efficient and Accurate
Signal Integrity Verification of Single Interconnect Lines},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1536--1545},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2196277},
doi = {10.1109/TCAD.2012.2196277},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimKE12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KimLM12,
author = {Myung{-}Chul Kim and
Dongjin Lee and
Igor L. Markov},
title = {SimPL: An Effective Placement Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {50--60},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2170567},
doi = {10.1109/TCAD.2011.2170567},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KimLM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KnechtelML12,
author = {Johann Knechtel and
Igor L. Markov and
Jens Lienig},
title = {Assembling 2-D Blocks Into 3-D Chips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {228--241},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2174640},
doi = {10.1109/TCAD.2011.2174640},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KnechtelML12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KochteEW12,
author = {Michael A. Kochte and
Melanie Elm and
Hans{-}Joachim Wunderlich},
title = {Accurate X-Propagation for Test Applications by SAT-Based Reasoning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1908--1919},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2210422},
doi = {10.1109/TCAD.2012.2210422},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/KochteEW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/KongP12,
author = {Byeong Yong Kong and
In{-}Cheol Park},
title = {{FIR} Filter Synthesis Based on Interleaved Processing of Coefficient
Generation and Multiplier-Block Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1169--1179},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2190826},
doi = {10.1109/TCAD.2012.2190826},
timestamp = {Mon, 05 Feb 2024 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/KongP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LakN12,
author = {Zahra Lak and
Nicola Nicolici},
title = {On Using On-Chip Clock Tuning Elements to Address Delay Degradation
Due to Circuit Aging},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1845--1856},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2209883},
doi = {10.1109/TCAD.2012.2209883},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LakN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeGD12,
author = {Hoang Minh Le and
Daniel Gro{\ss}e and
Rolf Drechsler},
title = {Automatic {TLM} Fault Localization for SystemC},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1249--1262},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2188800},
doi = {10.1109/TCAD.2012.2188800},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeGD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeCBKJ12,
author = {Jongwon Lee and
Duo Chen and
Venkataramanan Balakrishnan and
Cheng{-}Kok Koh and
Dan Jiao},
title = {A Quadratic Eigenvalue Solver of Linear Complexity for 3-D Electromagnetics-Based
Analysis of Large-Scale Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {380--390},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2170989},
doi = {10.1109/TCAD.2011.2170989},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeCBKJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeHB12,
author = {Kuen{-}Jong Lee and
Tong{-}Yu Hsieh and
Melvin A. Breuer},
title = {Efficient Overdetection Elimination of Acceptable Faults for Yield
Improvement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {754--764},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2179036},
doi = {10.1109/TCAD.2011.2179036},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeHB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeLL12,
author = {Mu{-}Shun Matt Lee and
Wei{-}Ting Liao and
Chien{-}Nan Jimmy Liu},
title = {Levelized High-Level Current Model of Logic Blocks for Dynamic Supply
Noise Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {845--857},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2182766},
doi = {10.1109/TCAD.2012.2182766},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeLL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeM12,
author = {Dongjin Lee and
Igor L. Markov},
title = {Obstacle-Aware Clock-Tree Shaping During Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {205--216},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2173490},
doi = {10.1109/TCAD.2011.2173490},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeR12,
author = {Dongsoo Lee and
Kaushik Roy},
title = {Viterbi-Based Efficient Test Data Compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {610--619},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2172609},
doi = {10.1109/TCAD.2011.2172609},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeSC12,
author = {Ming{-}Chao Lee and
Yiyu Shi and
Shih{-}Chieh Chang},
title = {Efficient Wakeup Scheduling Considering Both Resource Usage and Timing
Budget for Power Gating Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1041--1049},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2187205},
doi = {10.1109/TCAD.2012.2187205},
timestamp = {Tue, 13 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LeeSC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeeTLC12,
author = {Lung{-}Jen Lee and
Wang{-}Dauh Tseng and
Rung{-}Bin Lin and
Cheng{-}Ho Chang},
title = {{\textdollar}2\{n\}{\textdollar} Pattern Run-Length for Test Data
Compression},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {644--648},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2176733},
doi = {10.1109/TCAD.2011.2176733},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeeTLC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LevantinoM12,
author = {Salvatore Levantino and
Paolo Maffezzoni},
title = {Computing the Perturbation Projection Vector of Oscillators via Frequency
Domain Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1499--1507},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2194493},
doi = {10.1109/TCAD.2012.2194493},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LevantinoM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LeviLTR12,
author = {Timoth{\'{e}}e Levi and
No{\"{e}}lle Lewis and
Jean Tomas and
Sylvie Renaud},
title = {Application of IP-Based Analog Platforms in the Design of Neuromimetic
Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1629--1641},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2204992},
doi = {10.1109/TCAD.2012.2204992},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LeviLTR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiCS12,
author = {Bing Li and
Ning Chen and
Ulf Schlichtmann},
title = {Statistical Timing Analysis for Latch-Controlled Circuits With Reduced
Iterations and Graph Transformations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1670--1683},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2202393},
doi = {10.1109/TCAD.2012.2202393},
timestamp = {Tue, 29 Dec 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiCS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiL12,
author = {Katherine Shu{-}Min Li and
Yi{-}Yu Liao},
title = {Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1930--1934},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2208644},
doi = {10.1109/TCAD.2012.2208644},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiZS12,
author = {Zhuo Li and
Nancy Ying Zhou and
Weiping Shi},
title = {{\textdollar}O(mn){\textdollar} Time Algorithm for Optimal Buffer
Insertion of Nets With {\textdollar}m{\textdollar} Sinks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {437--441},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2174639},
doi = {10.1109/TCAD.2011.2174639},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiZS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiangKWM12,
author = {Yu{-}Yi Liang and
Tien{-}Yu Kuo and
Shao{-}Huan Wang and
Wai{-}Kei Mak},
title = {ALMmap: Technology Mapping for FPGAs With Adaptive Logic Modules},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1134--1139},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2187525},
doi = {10.1109/TCAD.2012.2187525},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiangKWM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinLCHC12,
author = {Cheng{-}Wu Lin and
Jai{-}Ming Lin and
Yen{-}Chih Chiu and
Chun{-}Po Huang and
Soon{-}Jyh Chang},
title = {Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor
Arrays Considering Dummy Capacitors},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1789--1802},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2204993},
doi = {10.1109/TCAD.2012.2204993},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinLCHC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinLCST12,
author = {Chung{-}Wei Lin and
Po{-}Wei Lee and
Yao{-}Wen Chang and
Chin{-}Fang Shen and
Wei{-}Chih Tseng},
title = {An Efficient Pre-Assignment Routing Algorithm for Flip-Chip Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {878--889},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2181511},
doi = {10.1109/TCAD.2011.2181511},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinLCST12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LinPBNLI12,
author = {Yen{-}Tzu Lin and
Osei Poku and
R. D. (Shawn) Blanton and
Phil Nigh and
Peter Lloyd and
Vikram Iyengar},
title = {Physically-Aware N-Detect Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {308--321},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2168526},
doi = {10.1109/TCAD.2011.2168526},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LinPBNLI12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuCLJ12,
author = {Hsiou{-}Yuan Liu and
Yen{-}Cheng Chou and
Chen{-}Hsuan Lin and
Jie{-}Hong R. Jiang},
title = {Automatic Decoder Synthesis: Methods and Case Studies},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1319--1331},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2191288},
doi = {10.1109/TCAD.2012.2191288},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuCLJ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuDZRG12,
author = {Bo Liu and
No{\"{e}}l Deferm and
Dixian Zhao and
Patrick Reynaert and
Georges G. E. Gielen},
title = {An Efficient High-Frequency Linear {RF} Amplifier Synthesis Method
Based on Evolutionary Computation and Machine Learning Techniques},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {981--993},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2187207},
doi = {10.1109/TCAD.2012.2187207},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuDZRG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuKLLWY12,
author = {Chih{-}Hung Liu and
Sy{-}Yen Kuo and
D. T. Lee and
Chun{-}Syun Lin and
Jung{-}Hung Weng and
Shih{-}Yi Yuan},
title = {Obstacle-Avoiding Rectilinear Steiner Tree Construction: {A} Steiner-Point-Based
Algorithm},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1050--1060},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2185050},
doi = {10.1109/TCAD.2012.2185050},
timestamp = {Tue, 14 Sep 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuKLLWY12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuSTV12,
author = {Lingyi Liu and
David Sheridan and
William Tuohy and
Shobha Vasudevan},
title = {A Technique for Test Coverage Closure Using GoldMine},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {790--803},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2177461},
doi = {10.1109/TCAD.2011.2177461},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LiuSTV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuX12,
author = {Xiao Liu and
Qiang Xu},
title = {On Signal Selection for Visibility Enhancement in Trace-Based Post-Silicon
Validation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1263--1274},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2189395},
doi = {10.1109/TCAD.2012.2189395},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiuX12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LiuX12a,
author = {Xiao Liu and
Qiang Xu},
title = {On X-Variable Filling and Flipping for Capture-Power Reduction in
Linear Decompressor-Based Test Compression Environment},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1743--1753},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2201481},
doi = {10.1109/TCAD.2012.2201481},
timestamp = {Tue, 21 Mar 2023 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/LiuX12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuMT12,
author = {Jianchao Lu and
Xiaomi Mao and
Baris Taskin},
title = {Integrated Clock Mesh Synthesis With Incremental Register Placement},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {217--227},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2173491},
doi = {10.1109/TCAD.2011.2173491},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuMT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/LuWTC12,
author = {Shyue{-}Kung Lu and
Zhen{-}Yu Wang and
Yi{-}Ming Tsai and
Jiann{-}Liang Chen},
title = {Efficient Built-In Self-Repair Techniques for Multiple Repairable
Embedded RAMs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {620--629},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2170569},
doi = {10.1109/TCAD.2011.2170569},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/LuWTC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Maffezzoni12,
author = {Paolo Maffezzoni},
title = {Stochastic Analysis of Switched-Capacitor Circuits for Sampled Data
Converters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {432--436},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2170570},
doi = {10.1109/TCAD.2011.2170570},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Maffezzoni12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MaffezzoniL12,
author = {Paolo Maffezzoni and
Salvatore Levantino},
title = {Phase-Noise Analysis and Simulation of {LC} Oscillator-Based Injection-Locked
Frequency Dividers},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1925--1929},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2205927},
doi = {10.1109/TCAD.2012.2205927},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MaffezzoniL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MajumderBPK12,
author = {Turbo Majumder and
Michael Edward Borgens and
Partha Pratim Pande and
Ananth Kalyanaraman},
title = {On-Chip Network-Enabled Multicore Platforms Targeting Maximum Likelihood
Phylogeny Reconstruction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1061--1073},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2188401},
doi = {10.1109/TCAD.2012.2188401},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MajumderBPK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MakLCW12,
author = {Wai{-}Kei Mak and
Yu{-}Chen Lin and
Chris Chu and
Ting{-}Chi Wang},
title = {Pad Assignment for Die-Stacking System-in-Package Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1711--1722},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2202395},
doi = {10.1109/TCAD.2012.2202395},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MakLCW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MangassarianVN12,
author = {Hratch Mangassarian and
Andreas G. Veneris and
Farid N. Najm},
title = {Maximum Circuit Activity Estimation Using Pseudo-Boolean Satisfiability},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {271--284},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2169259},
doi = {10.1109/TCAD.2011.2169259},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MangassarianVN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MarculescuL12,
author = {Diana Marculescu and
Peng Li},
title = {Guest Editorial Special Section on {PAR-CAD:} Parallel {CAD} Algorithms
and {CAD} for Parallel Architectures/Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {7--8},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2175038},
doi = {10.1109/TCAD.2011.2175038},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MarculescuL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MarianiPZS12,
author = {Giovanni Mariani and
Gianluca Palermo and
Vittorio Zaccaria and
Cristina Silvano},
title = {{OSCAR:} An Optimization Methodology Exploiting Spatial Correlation
in Multicore Design Spaces},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {740--753},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2177457},
doi = {10.1109/TCAD.2011.2177457},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MarianiPZS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MelamedTHPFSD12,
author = {Samson Melamed and
Thorlindur Thorolfsson and
T. Robert Harris and
Shivam Priyadarshi and
Paul D. Franzon and
Michael B. Steer and
W. Rhett Davis},
title = {Junction-Level Thermal Analysis of 3-D Integrated Circuits Using High
Definition Power Blurring},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {676--689},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2180384},
doi = {10.1109/TCAD.2011.2180384},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MelamedTHPFSD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukherjeeD12,
author = {Subhankar Mukherjee and
Pallab Dasgupta},
title = {Assertion Aware Sampling Refinement: {A} Mixed-Signal Perspective},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1772--1776},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2202394},
doi = {10.1109/TCAD.2012.2202394},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukherjeeD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukherjeeD12a,
author = {Subhankar Mukherjee and
Pallab Dasgupta},
title = {Computing Minimal Debugging Windows in Failure Traces of {AMS} Assertions},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1776--1781},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2203599},
doi = {10.1109/TCAD.2012.2203599},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukherjeeD12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/MukherjeeFBL12,
author = {Parijat Mukherjee and
G. Peter Fang and
Rod Burt and
Peng Li},
title = {Efficient Identification of Unstable Loops in Large Linear Analog
Integrated Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1332--1345},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2194492},
doi = {10.1109/TCAD.2012.2194492},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/MukherjeeFBL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NasseryEOV12,
author = {Afsaneh Nassery and
Osman Emir Erol and
Sule Ozev and
Marian Verhelst},
title = {Test Signal Development and Analysis for {OFDM} Systems {RF} Front-End
Parameter Extraction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {958--967},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2183370},
doi = {10.1109/TCAD.2012.2183370},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NasseryEOV12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/NatarajanCBSCSTB12,
author = {Vishwanath Natarajan and
Hyun Woo Choi and
Aritra Banerjee and
Shreyas Sen and
Abhijit Chatterjee and
Ganesh Srinivasan and
Friedrich Taenzler and
Soumendu Bhattacharya},
title = {Low Cost {EVM} Testing of Wireless {RF} SoC Front-Ends Using Multitones},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1088--1101},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2187652},
doi = {10.1109/TCAD.2012.2187652},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/NatarajanCBSCSTB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OhCH12,
author = {Dongkeun Oh and
Charlie Chung{-}Ping Chen and
Yu Hen Hu},
title = {Efficient Thermal Simulation for 3-D {IC} With Thermal Through-Silicon
Vias},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1767--1771},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2196435},
doi = {10.1109/TCAD.2012.2196435},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/OhCH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/OzdalBH12,
author = {Muhammet Mustafa Ozdal and
Steven M. Burns and
Jiang Hu},
title = {Algorithms for Gate Sizing and Device Parameter Selection for High-Performance
Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1558--1571},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2196279},
doi = {10.1109/TCAD.2012.2196279},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/OzdalBH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PaikHKS12,
author = {Seungwhun Paik and
Inhak Han and
Sangmin Kim and
Youngsoo Shin},
title = {Clock Gating Synthesis of Pulsed-Latch Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1019--1030},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2185235},
doi = {10.1109/TCAD.2012.2185235},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PaikHKS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ParkYL12,
author = {Hyunsun Park and
Sungjoo Yoo and
Sunggu Lee},
title = {A Multistep Tag Comparison Method for a Low-Power {L2} Cache},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {559--572},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2177458},
doi = {10.1109/TCAD.2011.2177458},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ParkYL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PassasKP12,
author = {Giorgos Passas and
Manolis Katevenis and
Dionisios N. Pnevmatikatos},
title = {Crossbar NoCs Are Scalable Beyond 100 Nodes},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {573--585},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2176730},
doi = {10.1109/TCAD.2011.2176730},
timestamp = {Wed, 07 Dec 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/PassasKP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pedram12,
author = {Massoud Pedram},
title = {Energy-Efficient Datacenters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1465--1484},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2212898},
doi = {10.1109/TCAD.2012.2212898},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pedram12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PoikonenLL12,
author = {Jussi H. Poikonen and
Eero Lehtonen and
Mika Laiho},
title = {On Synthesis of Boolean Expressions for Memristive Devices Using Sequential
Implication Logic},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1129--1134},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2187524},
doi = {10.1109/TCAD.2012.2187524},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PoikonenLL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz12,
author = {Irith Pomeranz},
title = {Multipattern Scan-Based Test Sets With Small Numbers of Primary Input
Sequences},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {322--326},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2170070},
doi = {10.1109/TCAD.2011.2170070},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz12a,
author = {Irith Pomeranz},
title = {Multicycle Tests With Constant Primary Input Vectors for Increased
Fault Coverage},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1428--1438},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2193583},
doi = {10.1109/TCAD.2012.2193583},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Pomeranz12b,
author = {Irith Pomeranz},
title = {A Metric for Identifying Detectable Path Delay Faults},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1734--1742},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2201482},
doi = {10.1109/TCAD.2012.2201482},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Pomeranz12b.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/PriyadarshiSKDDFS12,
author = {Shivam Priyadarshi and
Christopher S. Saunders and
Nikhil Kriplani and
Harun Demircioglu and
W. Rhett Davis and
Paul D. Franzon and
Michael B. Steer},
title = {Parallel Transient Simulation of Multiphysics Circuits Using Delay-Based
Partitioning},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1522--1535},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2201156},
doi = {10.1109/TCAD.2012.2201156},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/PriyadarshiSKDDFS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QianRKG12,
author = {Haifeng Qian and
Phillip J. Restle and
Joseph N. Kozhaya and
Clifford L. Gunion},
title = {Subtractive Router for Tree-Driven-Grid Clocks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {868--877},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2182767},
doi = {10.1109/TCAD.2012.2182767},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QianRKG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/QinWM12,
author = {Xiaoke Qin and
Weixun Wang and
Prabhat Mishra},
title = {{TCEC:} Temperature and Energy-Constrained Scheduling in Real-Time
Multitasking Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1159--1168},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2190824},
doi = {10.1109/TCAD.2012.2190824},
timestamp = {Tue, 07 May 2024 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/QinWM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RabenaltRPG12,
author = {Thomas Rabenalt and
Michael Richter and
Frank Poehl and
Michael G{\"{o}}ssel},
title = {Highly Efficient Test Response Compaction Using a Hierarchical X-Masking
Technique},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {950--957},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2181847},
doi = {10.1109/TCAD.2011.2181847},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RabenaltRPG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RavishankarAK12,
author = {Chirag Ravishankar and
Jason Helge Anderson and
Andrew A. Kennings},
title = {{FPGA} Power Reduction by Guarded Evaluation Considering Logic Architecture},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1305--1318},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2192478},
doi = {10.1109/TCAD.2012.2192478},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RavishankarAK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/RenLCSFKZD12,
author = {Pengju Ren and
Mieszko Lis and
Myong Hyon Cho and
Keun Sup Shim and
Christopher W. Fletcher and
Omer Khan and
Nanning Zheng and
Srinivas Devadas},
title = {{HORNET:} {A} Cycle-Level Multicore Simulator},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {890--903},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2184760},
doi = {10.1109/TCAD.2012.2184760},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/RenLCSFKZD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SalamyR12,
author = {Hassan A. Salamy and
J. Ramanujam},
title = {An Effective Solution to Task Scheduling and Memory Partitioning for
Multiprocessor System-on-Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {717--725},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2181848},
doi = {10.1109/TCAD.2011.2181848},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SalamyR12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Sapatnekar12,
author = {Sachin S. Sapatnekar},
title = {Editorial},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {1},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2178171},
doi = {10.1109/TCAD.2011.2178171},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Sapatnekar12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SarbisheiRZ12,
author = {Omid Sarbishei and
Katarzyna Radecka and
Zeljko Zilic},
title = {Analytical Optimization of Bit-Widths in Fixed-Point {LTI} Systems},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {343--355},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2170988},
doi = {10.1109/TCAD.2011.2170988},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SarbisheiRZ12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SeomunSS12,
author = {Jun Seomun and
Insup Shin and
Youngsoo Shin},
title = {Synthesis of Active-Mode Power-Gating Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {391--403},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2171963},
doi = {10.1109/TCAD.2011.2171963},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SeomunSS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Shelar12,
author = {Rupesh S. Shelar},
title = {A Fast and Near-Optimal Clustering Algorithm for Low-Power Clock Tree
Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1781--1786},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2206592},
doi = {10.1109/TCAD.2012.2206592},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Shelar12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShenHP12,
author = {Hao Shen and
Mian Muhammad Hamayun and
Fr{\'{e}}d{\'{e}}ric P{\'{e}}trot},
title = {Native Simulation of MPSoC Using Hardware-Assisted Virtualization},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1074--1087},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2187526},
doi = {10.1109/TCAD.2012.2187526},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShenHP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShenQWPZL12,
author = {ShengYu Shen and
Ying Qin and
Kefei Wang and
Zhengbin Pang and
Jianmin Zhang and
Sikun Li},
title = {Inferring Assertion for Complementary Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1288--1292},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2190735},
doi = {10.1109/TCAD.2012.2190735},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShenQWPZL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShiZS12,
author = {Bing Shi and
Yufu Zhang and
Ankur Srivastava},
title = {Accelerating Gate Sizing Using Graphics Processing Units},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {160--164},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2164539},
doi = {10.1109/TCAD.2011.2164539},
timestamp = {Thu, 18 Nov 2021 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ShiZS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ShihC12,
author = {Xin{-}Wei Shih and
Yao{-}Wen Chang},
title = {Fast Timing-Model Independent Buffered Clock-Tree Synthesis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1393--1404},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2191554},
doi = {10.1109/TCAD.2012.2191554},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ShihC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinghRLCO12,
author = {Ashish Kumar Singh and
Kareem Ragab and
Mario Lok and
Constantine Caramanis and
Michael Orshansky},
title = {Predictable Equation-Based Analog Optimization Based on Explicit Capture
of Modeling Error Statistics},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1485--1498},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2199115},
doi = {10.1109/TCAD.2012.2199115},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinghRLCO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SinhaP12,
author = {Rohit Sinha and
Hiren D. Patel},
title = {synASM: {A} High-Level Synthesis Framework With Support for Parallel
and Timed Constructs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1508--1521},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2198474},
doi = {10.1109/TCAD.2012.2198474},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SinhaP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SmyG12,
author = {Tom J. Smy and
Pavan K. Gunupudi},
title = {Robust Simulation of Opto-Electronic Systems by Alternating Complex
Envelope Representations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1139--1143},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2113770},
doi = {10.1109/TCAD.2011.2113770},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SmyG12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SridharVRA12,
author = {Arvind Sridhar and
Alessandro Vincenzi and
Martino Ruggiero and
David Atienza},
title = {Neural Network-Based Thermal Simulation of Integrated Circuits on
GPUs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {23--36},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2174236},
doi = {10.1109/TCAD.2011.2174236},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SridharVRA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SrinivasanGK12,
author = {Sudarshan Srinivasan and
Kunal P. Ganeshpure and
Sandip Kundu},
title = {A Wavelet-Based Spatio-Temporal Heat Dissipation Model for Reordering
of Program Phases to Produce Temperature Extremes in a Chip},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1867--1880},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2208643},
doi = {10.1109/TCAD.2012.2208643},
timestamp = {Mon, 28 Aug 2023 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SrinivasanGK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/Stratigopoulos12,
author = {Haralampos{-}G. D. Stratigopoulos},
title = {Test Metrics Model for Analog Test Development},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1116--1128},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2185931},
doi = {10.1109/TCAD.2012.2185931},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/Stratigopoulos12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/SunFDL12,
author = {Shupeng Sun and
Yamei Feng and
Changdao Dong and
Xin Li},
title = {Efficient {SRAM} Failure Rate Prediction via Gibbs Sampling},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1831--1844},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2209884},
doi = {10.1109/TCAD.2012.2209884},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/SunFDL12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TamB12,
author = {Wing Chiu Tam and
R. D. (Shawn) Blanton},
title = {{SLIDER:} Simulation of Layout-Injected Defects for Electrical Responses},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {918--929},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2184108},
doi = {10.1109/TCAD.2012.2184108},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TamB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/TianTYS12,
author = {Haitong Tian and
Wai{-}Chung Tang and
Evangeline F. Y. Young and
Cliff C. N. Sze},
title = {Postgrid Clock Routing for High Performance Microprocessor Designs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {255--259},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2170688},
doi = {10.1109/TCAD.2011.2170688},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/TianTYS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VillenaS12,
author = {Jorge Fernandez Villena and
Lu{\'{\i}}s Miguel Silveira},
title = {Exploiting Parallelism for Improved Automation of Multidimensional
Model Order Reduction},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {37--49},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2167510},
doi = {10.1109/TCAD.2011.2167510},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VillenaS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ViraraghavanPW12,
author = {Janakiraman Viraraghavan and
Shrinivas J. Pandharpure and
Josef Watts},
title = {Statistical Compact Model Extraction: {A} Neural Network Approach},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {12},
pages = {1920--1924},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2207955},
doi = {10.1109/TCAD.2012.2207955},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ViraraghavanPW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/VitkovskiySN12,
author = {Arseniy Vitkovskiy and
Vassos Soteriou and
Chrysostomos Nicopoulos},
title = {A Dynamically Adjusting Gracefully Degrading Link-Level Fault-Tolerant
Mechanism for NoCs},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1235--1248},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2188801},
doi = {10.1109/TCAD.2012.2188801},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/VitkovskiySN12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WanC12,
author = {Lu Wan and
Deming Chen},
title = {Analysis of Digital Circuit Dynamic Behavior With Timed Ternary Decision
Diagrams for Better-Than-Worst-Case Design},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {662--675},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2181512},
doi = {10.1109/TCAD.2011.2181512},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WanC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangHCPW12,
author = {Yuanzhe Wang and
Xiang Hu and
Chung{-}Kuan Cheng and
Grantham K. H. Pang and
Ngai Wong},
title = {A Realistic Early-Stage Power Grid Verification Algorithm Based on
Hierarchical Constraints},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {109--120},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2167328},
doi = {10.1109/TCAD.2011.2167328},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangHCPW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangHCPW12a,
author = {Yuanzhe Wang and
Xiang Hu and
Chung{-}Kuan Cheng and
Grantham K. H. Pang and
Ngai Wong},
title = {Corrigendum to "A Realistic Early-Stage Power Grid Verification Algorithm
Based on Hierarchical Constraints"},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {452},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2186340},
doi = {10.1109/TCAD.2012.2186340},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangHCPW12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangLKM12,
author = {Shao{-}Huan Wang and
Yu{-}Yi Liang and
Tien{-}Yu Kuo and
Wai{-}Kei Mak},
title = {{ISPD11:} Power-Driven Flip-Flop Merging and Relocation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {180--191},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2177460},
doi = {10.1109/TCAD.2011.2177460},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WangLKM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WangZKSPW12,
author = {Yuanzhe Wang and
Zheng Zhang and
Cheng{-}Kok Koh and
Guoyong Shi and
Grantham K. H. Pang and
Ngai Wong},
title = {Passivity Enforcement for Descriptor Systems Via Matrix Pencil Perturbation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {532--545},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2174638},
doi = {10.1109/TCAD.2011.2174638},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/WangZKSPW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WeiCC12,
author = {Chun{-}Jen Wei and
Howard Chen and
Sao{-}Jie Chen},
title = {Design and Implementation of Block-Based Partitioning for Parallel
Flip-Chip Power-Grid Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {370--379},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2173489},
doi = {10.1109/TCAD.2011.2173489},
timestamp = {Fri, 24 Jun 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WeiCC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WelpKK12,
author = {Tobias Welp and
Nathan Kitchen and
Andreas Kuehlmann},
title = {Hardware Acceleration for Constraint Solving for Random Simulation},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {5},
pages = {779--789},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2179037},
doi = {10.1109/TCAD.2011.2179037},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WelpKK12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/WengCC12,
author = {Shih{-}Hung Weng and
Quan Chen and
Chung{-}Kuan Cheng},
title = {Time-Domain Analysis of Large-Scale Circuits by Matrix Exponential
Method With Adaptive Control},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1180--1193},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2189396},
doi = {10.1109/TCAD.2012.2189396},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/WengCC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XieD12,
author = {Lin Xie and
Azadeh Davoodi},
title = {Post-Silicon Failing-Path Isolation Incorporating the Effects of Process
Variations},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {7},
pages = {1008--1018},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2187206},
doi = {10.1109/TCAD.2012.2187206},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XieD12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/XuSSB12,
author = {Chuan Xu and
Navin Srivastava and
Roberto Suaya and
Kaustav Banerjee},
title = {Fast High-Frequency Impedance Extraction of Horizontal Interconnects
and Inductors in 3-D ICs With Multiple Substrates},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {11},
pages = {1698--1710},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2203598},
doi = {10.1109/TCAD.2012.2203598},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/XuSSB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YanW12,
author = {Tan Yan and
Martin D. F. Wong},
title = {Correctly Model the Diagonal Capacity in Escape Routing},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {285--293},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2169258},
doi = {10.1109/TCAD.2011.2169258},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YanW12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangO12,
author = {Chengmo Yang and
Alex Orailoglu},
title = {Tackling Resource Variations Through Adaptive Multicore Execution
Frameworks},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {132--145},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2166829},
doi = {10.1109/TCAD.2011.2166829},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangT12,
author = {Joon{-}Sung Yang and
Nur A. Touba},
title = {Efficient Trace Signal Selection for Silicon Debug by Error Transmission
Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {3},
pages = {442--446},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2171184},
doi = {10.1109/TCAD.2011.2171184},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangT12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YangT12a,
author = {Joon{-}Sung Yang and
Nur A. Touba},
title = {X-Canceling {MISR} Architectures for Output Response Compaction With
Unknown Values},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1417--1427},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2193579},
doi = {10.1109/TCAD.2012.2193579},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YangT12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YilmazO12,
author = {Ender Yilmaz and
Sule Ozev},
title = {Test Application for Analog/RF Circuits With Low Computational Burden},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {968--979},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2181846},
doi = {10.1109/TCAD.2011.2181846},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YilmazO12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuB12,
author = {Xiaochun Yu and
R. D. (Shawn) Blanton},
title = {Diagnosis-Assisted Adaptive Test},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {9},
pages = {1405--1416},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2193580},
doi = {10.1109/TCAD.2012.2193580},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuB12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuB12a,
author = {Xiaochun Yu and
Ronald D. Blanton},
title = {Improving Diagnosis Through Failing Behavior Identification},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {10},
pages = {1614--1625},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2196278},
doi = {10.1109/TCAD.2012.2196278},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuB12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YuanYP12,
author = {Kun Yuan and
Bei Yu and
David Z. Pan},
title = {E-Beam Lithography Stencil Planning and Optimization With Overlapped
Characters},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {167--179},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2179041},
doi = {10.1109/TCAD.2011.2179041},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YuanYP12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/YunKH12,
author = {Dukyoung Yun and
Sungchan Kim and
Soonhoi Ha},
title = {A Parallel Simulation Technique for Multicore Embedded Systems and
Its Performance Analysis},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {121--131},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2167329},
doi = {10.1109/TCAD.2011.2167329},
timestamp = {Thu, 24 Sep 2020 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/YunKH12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhangLPWWWM12,
author = {Jie Zhang and
Albert Lin and
Nishant Patil and
Hai Wei and
Lan Wei and
H.{-}S. Philip Wong and
Subhasish Mitra},
title = {Carbon Nanotube Robust Digital {VLSI}},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {4},
pages = {453--471},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2187527},
doi = {10.1109/TCAD.2012.2187527},
timestamp = {Sun, 25 Jul 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhangLPWWWM12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoC12,
author = {Yang Zhao and
Krishnendu Chakrabarty},
title = {Simultaneous Optimization of Droplet Routing and Control-Pin Mapping
to Electrodes in Digital Microfluidic Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {2},
pages = {242--254},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2177836},
doi = {10.1109/TCAD.2011.2177836},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoC12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoC12a,
author = {Yang Zhao and
Krishnendu Chakrabarty},
title = {Cross-Contamination Avoidance for Droplet Routing in Digital Microfluidic
Biochips},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {817--830},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2183369},
doi = {10.1109/TCAD.2012.2183369},
timestamp = {Mon, 03 Jan 2022 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoC12a.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhaoTML12,
author = {Xin Zhao and
Jeremy R. Tolbert and
Saibal Mukhopadhyay and
Sung Kyu Lim},
title = {Variation-Aware Clock Network Design Methodology for Ultralow Voltage
{(ULV)} Circuits},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {8},
pages = {1222--1234},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2012.2190825},
doi = {10.1109/TCAD.2012.2190825},
timestamp = {Sun, 02 Oct 2022 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhaoTML12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhouGNA12,
author = {Yinghong Zhou and
Emad Gad and
Michel S. Nakhla and
Ramachandra Achar},
title = {Structural Characterization and Efficient Implementation Techniques
for {\textdollar}A{\textdollar}-Stable High-Order Integration Methods},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {1},
pages = {101--108},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2167326},
doi = {10.1109/TCAD.2011.2167326},
timestamp = {Thu, 14 Oct 2021 01:00:00 +0200},
biburl = {https://dblp.org/rec/journals/tcad/ZhouGNA12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/tcad/ZhuBGS12,
author = {Xue{-}Yang Zhu and
Twan Basten and
Marc Geilen and
Sander Stuijk},
title = {Efficient Retiming of Multirate {DSP} Algorithms},
journal = {{IEEE} Trans. Comput. Aided Des. Integr. Circuits Syst.},
volume = {31},
number = {6},
pages = {831--844},
year = {2012},
url = {https://doi.org/10.1109/TCAD.2011.2182352},
doi = {10.1109/TCAD.2011.2182352},
timestamp = {Mon, 26 Oct 2020 00:00:00 +0100},
biburl = {https://dblp.org/rec/journals/tcad/ZhuBGS12.bib},
bibsource = {dblp computer science bibliography, https://dblp.org}
}
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