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@article{DBLP:journals/ijrc/AliACFD19,
  author       = {Karim M. A. Ali and
                  Rabie Ben Atitallah and
                  Abdessamad Ait El Cadi and
                  Nizar Fakhfakh and
                  Jean{-}Luc Dekeyser},
  title        = {ViPar: High-Level Design Space Exploration for Parallel Video Processing
                  Architectures},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {4298013:1--4298013:19},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/4298013},
  doi          = {10.1155/2019/4298013},
  timestamp    = {Mon, 26 Oct 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ijrc/AliACFD19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/DasP19,
  author       = {Nitish Das and
                  Aruna Priya P.},
  title        = {{FPGA} Implementation of an Improved Reconfigurable {FSMIM} Architecture
                  Using Logarithmic Barrier Function Based Gradient Descent Approach},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {3727254:1--3727254:17},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/3727254},
  doi          = {10.1155/2019/3727254},
  timestamp    = {Fri, 16 Apr 2021 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/DasP19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/DinelliMRBF19,
  author       = {Gianmarco Dinelli and
                  Gabriele Meoni and
                  Emilio Rapuano and
                  Gionata Benelli and
                  Luca Fanucci},
  title        = {An FPGA-Based Hardware Accelerator for CNNs Using On-Chip Memories
                  Only: Design and Benchmarking with Intel Movidius Neural Compute Stick},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {7218758:1--7218758:13},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/7218758},
  doi          = {10.1155/2019/7218758},
  timestamp    = {Tue, 26 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ijrc/DinelliMRBF19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/FangIL19,
  author       = {Xin Fang and
                  Stratis Ioannidis and
                  Miriam Leeser},
  title        = {{SIFO:} Secure Computational Infrastructure Using {FPGA} Overlays},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {1439763:1--1439763:18},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/1439763},
  doi          = {10.1155/2019/1439763},
  timestamp    = {Wed, 20 Jan 2021 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ijrc/FangIL19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/GiorgiKP19,
  author       = {Roberto Giorgi and
                  Farnam Khalili and
                  Marco Procaccini},
  title        = {Translating Timing into an Architecture: The Synergy of COTSon and
                  {HLS} (Domain Expertise - Designing a Computer Architecture via {HLS)}},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {2624938:1--2624938:18},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/2624938},
  doi          = {10.1155/2019/2624938},
  timestamp    = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/GiorgiKP19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/KirchhoffKSF19,
  author       = {Michael Kirchhoff and
                  Philipp Kerling and
                  Detlef Streitferdt and
                  Wolfgang Fengler},
  title        = {A Real-Time Capable Dynamic Partial Reconfiguration System for an
                  Application-Specific Soft-Core Processor},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {4723838:1--4723838:14},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/4723838},
  doi          = {10.1155/2019/4723838},
  timestamp    = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/KirchhoffKSF19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/MacintoshBK19,
  author       = {Hamish J. Macintosh and
                  Jasmine Banks and
                  Neil A. Kelson},
  title        = {Implementing and Evaluating an Heterogeneous, Scalable, Tridiagonal
                  Linear System Solver with OpenCL to Target FPGAs, GPUs, and CPUs},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {3679839:1--3679839:13},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/3679839},
  doi          = {10.1155/2019/3679839},
  timestamp    = {Thu, 23 Jun 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/MacintoshBK19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/MahmudE19,
  author       = {Naveed Mahmud and
                  Esam El{-}Araby},
  title        = {Dimension Reduction Using Quantum Wavelet Transform on a High-Performance
                  Reconfigurable Computer},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {1949121:1--1949121:14},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/1949121},
  doi          = {10.1155/2019/1949121},
  timestamp    = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/MahmudE19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/NabiV19,
  author       = {Syed Waqar Nabi and
                  Wim Vanderbauwhede},
  title        = {Automatic Pipelining and Vectorization of Scientific Code for FPGAs},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {7348013:1--7348013:12},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/7348013},
  doi          = {10.1155/2019/7348013},
  timestamp    = {Tue, 16 Jun 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/NabiV19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/SkhiriFJSM19,
  author       = {Rym Skhiri and
                  Virginie Fresse and
                  Jean{-}Paul Jamont and
                  Beno{\^{\i}}t Suffran and
                  Jihene Malek},
  title        = {From {FPGA} to Support Cloud to Cloud of {FPGA:} State of the Art},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {8085461:1--8085461:17},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/8085461},
  doi          = {10.1155/2019/8085461},
  timestamp    = {Sat, 27 Apr 2024 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/SkhiriFJSM19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/Vipin19,
  author       = {Kizheppatt Vipin},
  title        = {AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based
                  NoC Implementation},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {7239858:1--7239858:9},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/7239858},
  doi          = {10.1155/2019/7239858},
  timestamp    = {Thu, 02 Apr 2020 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/journals/ijrc/Vipin19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@article{DBLP:journals/ijrc/ZhangL19,
  author       = {Ting Zhang and
                  Bin Liu},
  title        = {Exposing End-to-End Delay in Software-Defined Networking},
  journal      = {Int. J. Reconfigurable Comput.},
  volume       = {2019},
  pages        = {7363901:1--7363901:12},
  year         = {2019},
  url          = {https://doi.org/10.1155/2019/7363901},
  doi          = {10.1155/2019/7363901},
  timestamp    = {Mon, 28 Dec 2020 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/journals/ijrc/ZhangL19.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
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