Search dblp for Publications

export results for "toc:db/conf/slip/slip2021.bht:"

 download as .bib file

@inproceedings{DBLP:conf/slip/CaloBBBFTSP21,
  author       = {Giovanna Cal{\`{o}} and
                  Marina Barbiroli and
                  Gaetano Bellanca and
                  Davide Bertozzi and
                  Franco Fuschini and
                  Velio Tralli and
                  Giovanni Serafino and
                  Vincenzo Petruzzelli},
  title        = {Reconfigurable on-chip wireless interconnections through optical phased
                  arrays (Invited)},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {33--40},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00014},
  doi          = {10.1109/SLIP52707.2021.00014},
  timestamp    = {Fri, 21 Jan 2022 09:18:37 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/CaloBBBFTSP21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Campenhout21,
  author       = {Joris Van Campenhout},
  title        = {Silicon Photonics Technology for Terabit-scale Optical {I/O} (Invited)},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {41},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00015},
  doi          = {10.1109/SLIP52707.2021.00015},
  timestamp    = {Fri, 21 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Campenhout21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/ChengHHL21,
  author       = {Chung{-}Kuan Cheng and
                  Chia{-}Tung Ho and
                  Chester Holtz and
                  Bill Lin},
  title        = {Design and System Technology Co-Optimization Sensitivity Prediction
                  for {VLSI} Technology Development using Machine Learning},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {8--15},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00009},
  doi          = {10.1109/SLIP52707.2021.00009},
  timestamp    = {Mon, 01 Aug 2022 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/ChengHHL21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/ChoudharyJC21,
  author       = {Jitesh Choudhary and
                  Soumya J. and
                  Linga Reddy Cenkeramaddi},
  title        = {{RAMAN:} Reinforcement Learning Inspired Algorithm for Mapping Applications
                  onto Mesh Network-on-Chip},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {52--58},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00019},
  doi          = {10.1109/SLIP52707.2021.00019},
  timestamp    = {Mon, 05 Feb 2024 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/ChoudharyJC21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/JiangP21,
  author       = {Minmin Jiang and
                  Vasilis F. Pavlidis},
  title        = {Performance-Aware Interconnect Delay Insertion Against {EM} Side-Channel
                  Attacks},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {25--32},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00013},
  doi          = {10.1109/SLIP52707.2021.00013},
  timestamp    = {Fri, 21 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/JiangP21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Karnik21,
  author       = {Tanay Karnik},
  title        = {Recent Advances and Future Challenges in 2.5D/3D Heterogeneous Integration
                  (Invited)},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {x},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00007},
  doi          = {10.1109/SLIP52707.2021.00007},
  timestamp    = {Fri, 21 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Karnik21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Muck21,
  author       = {Tiago M{\"{u}}ck},
  title        = {Network-on-Chips for Future 3D Stacked Dies (Invited)},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {59},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00020},
  doi          = {10.1109/SLIP52707.2021.00020},
  timestamp    = {Fri, 21 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Muck21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Nagata21,
  author       = {Makoto Nagata},
  title        = {Chip Stacking and Packaging Technology Explorations for Hardware Security
                  (Invited)},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {24},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00012},
  doi          = {10.1109/SLIP52707.2021.00012},
  timestamp    = {Fri, 21 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Nagata21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Ramalingam21,
  author       = {Suresh Ramalingam},
  title        = {Enabling Chiplet Integration Beyond 7nm (Invited)},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {16},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00010},
  doi          = {10.1109/SLIP52707.2021.00010},
  timestamp    = {Fri, 21 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Ramalingam21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/SharifpourSR21,
  author       = {Babak Sharifpour and
                  Mohammad Sharifpour and
                  Midia Reshadi},
  title        = {SID-Mesh: Diagonal Mesh Topology for Silicon Interposer in 2.5D NoC
                  with Introducing a New Routing Algorithm},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {44--51},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00018},
  doi          = {10.1109/SLIP52707.2021.00018},
  timestamp    = {Fri, 21 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/SharifpourSR21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/SistoCCPBMM21,
  author       = {Giuliano Sisto and
                  Rongmei Chen and
                  Richard Chou and
                  Geert Van der Plas and
                  Eric Beyne and
                  Rod Metcalfe and
                  Dragomir Milojevic},
  title        = {Design And Sign-off Methodologies For Wafer-To-Wafer Bonded 3D-ICs
                  At Advanced Nodes (invited)},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {17--23},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00011},
  doi          = {10.1109/SLIP52707.2021.00011},
  timestamp    = {Sat, 30 Sep 2023 01:00:00 +0200},
  biburl       = {https://dblp.org/rec/conf/slip/SistoCCPBMM21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Thonnart21,
  author       = {Yvain Thonnart},
  title        = {Designing a Multi-Chiplet Manycore System using the {POPSTAR} Optical
                  NoC Architecture (Invited)},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {42},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00016},
  doi          = {10.1109/SLIP52707.2021.00016},
  timestamp    = {Fri, 21 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Thonnart21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/Vinnakota21,
  author       = {Bapi Vinnakota},
  title        = {The Open Domain-Specific Architecture: An Introduction (Invited)},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {43},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00017},
  doi          = {10.1109/SLIP52707.2021.00017},
  timestamp    = {Fri, 21 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/Vinnakota21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@inproceedings{DBLP:conf/slip/ZahedmaneshCZBC21,
  author       = {Houman Zahedmanesh and
                  Ivan Ciofi and
                  Odysseas Zografos and
                  Mustafa Badaroglu and
                  Kristof Croes},
  title        = {A Novel System-Level Physics-Based Electromigration Modelling Framework:
                  Application to the Power Delivery Network},
  booktitle    = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  pages        = {1--7},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021.00008},
  doi          = {10.1109/SLIP52707.2021.00008},
  timestamp    = {Fri, 21 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/ZahedmaneshCZBC21.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}

@proceedings{DBLP:conf/slip/2021,
  title        = {{ACM/IEEE} International Workshop on System Level Interconnect Prediction,
                  {SLIP} 2021, Munich, Germany, November 4, 2021},
  publisher    = {{IEEE}},
  year         = {2021},
  url          = {https://doi.org/10.1109/SLIP52707.2021},
  doi          = {10.1109/SLIP52707.2021},
  isbn         = {978-1-6654-0083-1},
  timestamp    = {Fri, 21 Jan 2022 00:00:00 +0100},
  biburl       = {https://dblp.org/rec/conf/slip/2021.bib},
  bibsource    = {dblp computer science bibliography, https://dblp.org}
}
a service of  Schloss Dagstuhl - Leibniz Center for Informatics

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.