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@inproceedings{DBLP:conf/heart/DuY19,
  author    = {Changdao Du and
               Yoshiki Yamaguchi},
  title     = {A High-Level Synthesis Design for a Scalable Hydrodynamic Simulation
               on OpenCL {FPGA} Platform},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {19:1--19:4},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337807},
  doi       = {10.1145/3337801.3337807},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/DuY19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/EgawaS0K19,
  author    = {Ryusuke Egawa and
               Ryoma Saito and
               Masayuki Sato and
               Hiroaki Kobayashi},
  title     = {A Layer-Adaptable Cache Hierarchy by a Multiple-layer Bypass Mechanism},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {12:1--12:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337820},
  doi       = {10.1145/3337801.3337820},
  timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/EgawaS0K19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/FirmansyahCFYB19,
  author    = {Iman Firmansyah and
               Changdao Du and
               Norihisa Fujita and
               Yoshiki Yamaguchi and
               Taisuke Boku},
  title     = {FPGA-based Implementation of Memory-Intensive Application using OpenCL},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {16:1--16:4},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337806},
  doi       = {10.1145/3337801.3337806},
  timestamp = {Thu, 26 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/FirmansyahCFYB19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/ForgetUDT19,
  author    = {Luc Forget and
               Yohann Uguen and
               Florent de Dinechin and
               David Thomas},
  title     = {A type-safe arbitrary precision arithmetic portability layer for {HLS}
               tools},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {5:1--5:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337809},
  doi       = {10.1145/3337801.3337809},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/ForgetUDT19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/GradyA19,
  author    = {Brett Grady and
               Jason Helge Anderson},
  title     = {Physical Design Considerations for Synthesizable Standard-Cell-Based
               FPGAs},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {3:1--3:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337818},
  doi       = {10.1145/3337801.3337818},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/GradyA19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/HuthmannAPST19,
  author    = {Jens Huthmann and
               Shin Abiko and
               Artur Podobas and
               Kentaro Sano and
               Hiroyuki Takizawa},
  title     = {Scaling Performance for N-Body Stream Computation with a Ring of FPGAs},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {10:1--10:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337813},
  doi       = {10.1145/3337801.3337813},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/HuthmannAPST19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KlemdEKHS19,
  author    = {Alexander Klemd and
               Marcel Eckert and
               Bernd Klauer and
               Jonas Hanselka and
               Delf Sachau},
  title     = {A Parameterizable Feedback FxLMS Architecture for {FPGA} Platforms},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {17:1--17:4},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337802},
  doi       = {10.1145/3337801.3337802},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/KlemdEKHS19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KonoN19,
  author    = {Fumiya Kono and
               Naohito Nakasato},
  title     = {Performance Evaluation of Tsunami Simulation Exploiting Temporal Parallelism
               on FPGAs using OpenCL},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {2:1--2:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337811},
  doi       = {10.1145/3337801.3337811},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/KonoN19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/ManevVKK19,
  author    = {Kristiyan Manev and
               Anuj Vaishnav and
               Charalampos Kritikakis and
               Dirk Koch},
  title     = {Scalable Filtering Modules for Database Acceleration on FPGAs},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {4:1--4:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337810},
  doi       = {10.1145/3337801.3337810},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/ManevVKK19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/MatsumotoNH19,
  author    = {Kazuya Matsumoto and
               Naohito Nakasato and
               Toshiaki Hishinuma},
  title     = {Effectiveness of performance tuning techniques for general matrix
               multiplication on the {PEZY-SC2}},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {8:1--8:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337817},
  doi       = {10.1145/3337801.3337817},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/MatsumotoNH19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/MiyajimaHMSS19,
  author    = {Takaaki Miyajima and
               Tomoya Hirao and
               Naoya Miyamoto and
               Jeongdo Son and
               Kentaro Sano},
  title     = {A software bridged data transfer on a {FPGA} cluster by using pipelining
               and InfiniBand verbs},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {11:1--11:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337808},
  doi       = {10.1145/3337801.3337808},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/MiyajimaHMSS19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/MiyazakiMK19,
  author    = {Hiromu Miyazaki and
               Junya Miura and
               Kenji Kise},
  title     = {An Efficient Instruction Fetch Architecture for a {RISC-V} Soft Processor
               on an {FPGA}},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {14:1--14:4},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337803},
  doi       = {10.1145/3337801.3337803},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/MiyazakiMK19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/NodaOIMFA19,
  author    = {Hiroyuki Noda and
               Manfred Orsztynowicz and
               Kensuke Iizuka and
               Takaaki Miyajima and
               Naoyuki Fujita and
               Hideharu Amano},
  title     = {An ARM-based heterogeneous {FPGA} accelerator for Hall thruster simulation},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {9:1--9:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337812},
  doi       = {10.1145/3337801.3337812},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/NodaOIMFA19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/OmidianL19,
  author    = {Hossein Omidian and
               Guy G. F. Lemieux},
  title     = {Software-based Dynamic Overlays Require Fast, Fine-grained Partial
               Reconfiguration},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {13:1--13:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337816},
  doi       = {10.1145/3337801.3337816},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/OmidianL19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/SunAA19,
  author    = {YuXi Sun and
               Akram Ben Ahmed and
               Hideharu Amano},
  title     = {Acceleration of Deep Recurrent Neural Networks with an {FPGA} cluster},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {18:1--18:4},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337804},
  doi       = {10.1145/3337801.3337804},
  timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/SunAA19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/TakaseMTT19,
  author    = {Hideki Takase and
               Tomoya Mori and
               Kazuyoshi Takagi and
               Naofumi Takagi},
  title     = {mROS: {A} Lightweight Runtime Environment for Robot Software Components
               onto Embedded Devices},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {7:1--7:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337815},
  doi       = {10.1145/3337801.3337815},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/TakaseMTT19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/VaishnavPK19,
  author    = {Anuj Vaishnav and
               Khoa Dang Pham and
               Dirk Koch},
  title     = {Heterogeneous Resource-Elastic Scheduling for {CPU+FPGA} Architectures},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {1:1--1:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337819},
  doi       = {10.1145/3337801.3337819},
  timestamp = {Wed, 25 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/VaishnavPK19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/WatanabeUZY19,
  author    = {Ryota Watanabe and
               Saika Ura and
               Qian Zhao and
               Takaichi Yoshida},
  title     = {Implementation of {FPGA} Building Platform as a Cloud Service},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {6:1--6:6},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337814},
  doi       = {10.1145/3337801.3337814},
  timestamp = {Tue, 04 Feb 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/WatanabeUZY19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/YamakuraHAMA19,
  author    = {Miho Yamakura and
               Kazuei Hironaka and
               Keita Azegami and
               Kazusa Musha and
               Hideharu Amano},
  title     = {The Evaluation of Partial Reconfiguration for a Multi-board {FPGA}
               System FiCSW},
  booktitle = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  pages     = {15:1--15:4},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801.3337805},
  doi       = {10.1145/3337801.3337805},
  timestamp = {Sun, 14 Jul 2019 18:04:14 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/YamakuraHAMA19.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/heart/2019,
  title     = {Proceedings of the 10th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2019, Nagasaki,
               Japan, June 6-7, 2019},
  publisher = {{ACM}},
  year      = {2019},
  url       = {https://doi.org/10.1145/3337801},
  doi       = {10.1145/3337801},
  isbn      = {978-1-4503-7255-8},
  timestamp = {Sun, 14 Jul 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/2019.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/0004SC18,
  author    = {David Wilson and
               Greg Stitt and
               James Coole},
  title     = {A Recurrently Generated Overlay Architecture for Rapid {FPGA} Application
               Development},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {4:1--4:6},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241797},
  doi       = {10.1145/3241793.3241797},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/0004SC18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/AfsharnejadYRCB18,
  author    = {Yasmin Afsharnejad and
               Abdul{-}Amir Yassine and
               Omar Ragheb and
               Paul Chow and
               Vaughn Betz},
  title     = {HLS-based {FPGA} Acceleration of Light Propagation Simulation in Turbid
               Media},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {11:1--11:6},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241804},
  doi       = {10.1145/3241793.3241804},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/AfsharnejadYRCB18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/BenoisNZEK18,
  author    = {Piero Rivera Benois and
               Patrick Nowak and
               Udo Z{\"{o}}lzer and
               Marcel Eckert and
               Bernd Klauer},
  title     = {Low-Latency {FIR} Filter Structures Targeting {FPGA} Platforms},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {14:1--14:7},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241807},
  doi       = {10.1145/3241793.3241807},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/BenoisNZEK18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/ChengSN18,
  author    = {Haoxuan Cheng and
               Shimpei Sato and
               Hiroki Nakahara},
  title     = {A Performance Per Power Efficient Object Detector on an {FPGA} for
               Robot Operating System {(ROS)}},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {20:1--20:4},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241814},
  doi       = {10.1145/3241793.3241814},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/ChengSN18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/ChoiLLCA18,
  author    = {Jongsok Choi and
               Ruolong Lian and
               Zhi Li and
               Andrew Canis and
               Jason Helge Anderson},
  title     = {Accelerating Memcached on {AWS} Cloud FPGAs},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {2:1--2:8},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241795},
  doi       = {10.1145/3241793.3241795},
  timestamp = {Fri, 17 Jan 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/ChoiLLCA18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/CrossGLS18,
  author    = {Andreea{-}Ingrid Cross and
               Liucheng Guo and
               Wayne Luk and
               Mark Salmon},
  title     = {{CJS:} Custom Jacobi Solver},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {9:1--9:6},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241802},
  doi       = {10.1145/3241793.3241802},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/CrossGLS18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/EhretJK18,
  author    = {Alan Ehret and
               Peter Jamieson and
               Michel A. Kinsy},
  title     = {Scalable Open-Source Reconfigurable Architecture for Bacterial Quorum
               Sensing Simulations},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {17:1--17:5},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241811},
  doi       = {10.1145/3241793.3241811},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/EhretJK18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/FujitaKYOBAYU18,
  author    = {Norihisa Fujita and
               Ryohei Kobayashi and
               Yoshiki Yamaguchi and
               Yuma Oobata and
               Taisuke Boku and
               Makito Abe and
               Kohji Yoshikawa and
               Masayuki Umemura},
  title     = {Accelerating Space Radiative Transfer on {FPGA} using OpenCL},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {6:1--6:7},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241799},
  doi       = {10.1145/3241793.3241799},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/FujitaKYOBAYU18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/GharanK18,
  author    = {Masoud Oveis Gharan and
               Gul N. Khan},
  title     = {Flexible Reconfigurable On-chip Networks for Multi-core SoCs},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {19:1--19:6},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241813},
  doi       = {10.1145/3241793.3241813},
  timestamp = {Fri, 27 Mar 2020 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/GharanK18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/JinF18,
  author    = {Zheming Jin and
               Hal Finkel},
  title     = {A Case Study of Integer Sum Reduction using Atomics},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {15:1--15:7},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241809},
  doi       = {10.1145/3241793.3241809},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/JinF18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/Kise18,
  author    = {Kenji Kise},
  title     = {Swap Based Merge Network for High Performance Sorting Accelerators},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {8:1--8:7},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241801},
  doi       = {10.1145/3241793.3241801},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/Kise18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KojimaAMODA18,
  author    = {Takuya Kojima and
               Naoki Ando and
               Yusuke Matshushita and
               Hayate Okuhara and
               Ng. Anh Vu Doan and
               Hideharu Amano},
  title     = {Real Chip Evaluation of a Low Power {CGRA} with Optimized Application
               Mapping},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {13:1--13:6},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241806},
  doi       = {10.1145/3241793.3241806},
  timestamp = {Sat, 19 Oct 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/KojimaAMODA18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/LeeUSS18,
  author    = {Jinpil Lee and
               Tomohiro Ueno and
               Mitsuhisa Sato and
               Kentaro Sano},
  title     = {High-productivity Programming and Optimization Framework for Stream
               Processing on {FPGA}},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {5:1--5:6},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241798},
  doi       = {10.1145/3241793.3241798},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/LeeUSS18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/LingAOBHDSJDFC18,
  author    = {Andrew C. Ling and
               Mohamed S. Abdelfattah and
               Shane O'Connell and
               Andrew Bitar and
               David Han and
               Roberto DiCecco and
               Suchit Subhaschandra and
               Chris N. Johnson and
               Dmitry Denisenko and
               Joshua Fender and
               Gordon R. Chiu},
  title     = {Harnessing Numerical Flexibility for Deep Learning on FPGAs},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {1:1--1:3},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241794},
  doi       = {10.1145/3241793.3241794},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/LingAOBHDSJDFC18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/MohsinP18,
  author    = {Mokhles A. Mohsin and
               Darshika G. Perera},
  title     = {An FPGA-Based Hardware Accelerator for K-Nearest Neighbor Classification
               for Machine Learning on Mobile Devices},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {16:1--16:7},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241810},
  doi       = {10.1145/3241793.3241810},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/MohsinP18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/SanaullahH18,
  author    = {Ahmed Sanaullah and
               Martin C. Herbordt},
  title     = {{FPGA} {HPC} using OpenCL: Case Study in 3D {FFT}},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {7:1--7:6},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241800},
  doi       = {10.1145/3241793.3241800},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/SanaullahH18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/SchmitzZ18,
  author    = {Jesse Schmitz and
               Lei Zhang},
  title     = {{FPGA} Hardware Implementation and Optimization for Neural Network
               based Chaotic System Design},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {18:1--18:6},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241812},
  doi       = {10.1145/3241793.3241812},
  timestamp = {Thu, 31 Oct 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/SchmitzZ18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/ShimodaSN18,
  author    = {Masayuki Shimoda and
               Shimpei Sato and
               Hiroki Nakahara},
  title     = {Power Efficient Object Detector with an Event-Driven Camera on an
               {FPGA}},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {10:1--10:6},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241803},
  doi       = {10.1145/3241793.3241803},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/ShimodaSN18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/SyrowikFB18,
  author    = {Bain Syrowik and
               Blair Fort and
               Stephen Dean Brown},
  title     = {Use of {CPU} Performance Counters for Accelerator Selection in HLS-Generated
               CPU-Accelerator Systems},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {12:1--12:6},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241805},
  doi       = {10.1145/3241793.3241805},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/SyrowikFB18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/WijesunderaPPHS18,
  author    = {Deshya Wijesundera and
               Alok Prakash and
               Thilina Perera and
               Kalindu Herath and
               Thambipillai Srikanthan},
  title     = {Wibheda+: Framework for Data Dependency-aware Multi-constrained Hardware-Software
               Partitioning in FPGA-based SoCs for IoT Applications},
  booktitle = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  pages     = {3:1--3:6},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793.3241796},
  doi       = {10.1145/3241793.3241796},
  timestamp = {Wed, 21 Nov 2018 12:44:16 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/WijesunderaPPHS18.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/heart/2018,
  title     = {Proceedings of the 9th International Symposium on Highly-Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2018, Toronto,
               ON, Canada, June 20-22, 2018},
  publisher = {{ACM}},
  year      = {2018},
  url       = {https://doi.org/10.1145/3241793},
  doi       = {10.1145/3241793},
  timestamp = {Wed, 21 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/2018.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/AmagasakiMKIS17,
  author    = {Motoki Amagasaki and
               Futoshi Murase and
               Morihiro Kuga and
               Masahiro Iida and
               Toshinori Sueyoshi},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {{FPGA} based {ASIC} Emulator with High Speed Optical Serial Links},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {18:1--18:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120913},
  doi       = {10.1145/3120895.3120913},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/AmagasakiMKIS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/ArndtSWPNB17,
  author    = {Oliver Jakob Arndt and
               Christian Spindeldreier and
               Kevin Wohnrade and
               Daniel Pfefferkorn and
               Martin Neuenhahn and
               Holger Blume},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {{FPGA} Accelerated NoC-Simulation: {A} Case Study on the Intel Xeon
               Phi Ringbus Topology},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {21:1--21:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120916},
  doi       = {10.1145/3120895.3120916},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/ArndtSWPNB17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/BaileyMS17,
  author    = {Donald G. Bailey and
               Faisal Mahmood and
               Ulf Skoglund},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Reducing the Cost of Removing Border Artefacts in Fourier Transforms},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {11:1--11:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120899},
  doi       = {10.1145/3120895.3120899},
  timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/BaileyMS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/EngelhardtS17,
  author    = {Nina Engelhardt and
               Hayden Kwok{-}Hay So},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Towards Flexible Automatic Generation of Graph Processing Gateware},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {5:1--5:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120896},
  doi       = {10.1145/3120895.3120896},
  timestamp = {Mon, 16 Sep 2019 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/conf/heart/EngelhardtS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/FukudaI17,
  author    = {Masahiro Fukuda and
               Yasushi Inoguchi},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Probabilistic Strategies Based on Staged {LSH} for Speedup of Audio
               Fingerprint Searching with Ten Million Scale Database},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {26:1--26:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120921},
  doi       = {10.1145/3120895.3120921},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/FukudaI17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/IshikawaYKMN17,
  author    = {Yuto Ishikawa and
               Keitaro Yanai and
               Keisuke Koike and
               Takefumi Miyoshi and
               Hironori Nakajo},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Hardware Acceleration with Multi-Threading of Java-Based High Level
               Synthesis Tool},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {8:1--8:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120912},
  doi       = {10.1145/3120895.3120912},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/IshikawaYKMN17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KalmsMG17,
  author    = {Lester Kalms and
               Khaled Mohamed and
               Diana G{\"{o}}hringer},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Accelerated Embedded {AKAZE} Feature Detection Algorithm on {FPGA}},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {10:1--10:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120898},
  doi       = {10.1145/3120895.3120898},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/KalmsMG17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KamasakaSO17,
  author    = {Ryo Kamasaka and
               Yuichiro Shibata and
               Kiyoshi Oguri},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {{FPGA} Implementation of {A} Graph Cut Algorithm For Stereo Vision},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {14:1--14:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120907},
  doi       = {10.1145/3120895.3120907},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/KamasakaSO17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KanedaSNHTA17,
  author    = {Takahiro Kaneda and
               Ryotaro Sakai and
               Naoki Nishikawa and
               Toshihiro Hanawa and
               Chiharu Tsuruta and
               Hideharu Amano},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Performance Evaluation of {PEACH3:} Field-Programmable Gate Array
               Switch for Tightly Coupled Accelerators},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {9:1--9:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120911},
  doi       = {10.1145/3120895.3120911},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/KanedaSNHTA17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KhanGHG17,
  author    = {Habib ul Hasan Khan and
               Thomas Grimm and
               Michael H{\"{u}}bner and
               Diana G{\"{o}}hringer},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Access Network Generation for Efficient Debugging of FPGAs},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {25:1--25:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120920},
  doi       = {10.1145/3120895.3120920},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/KhanGHG17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KoraeiJF17,
  author    = {Mostafa Koraei and
               Magnus Jahre and
               S. Omid Fatemi},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {{DTP:} Enabling Exhaustive Exploration of {FPGA} Temporal Partitions
               for Streaming {HPC} Applications},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {7:1--7:11},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120901},
  doi       = {10.1145/3120895.3120901},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/KoraeiJF17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/KugaFAIS17,
  author    = {Morihiro Kuga and
               Kansuke Fukuda and
               Motoki Amagasaki and
               Masahiro Iida and
               Toshinori Sueyoshi},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {High-level Synthesis based on Parallel Design Patterns using a Functional
               Language},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {23:1--23:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120918},
  doi       = {10.1145/3120895.3120918},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/KugaFAIS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/LiL17,
  author    = {Jiajun Li and
               Qiang Liu},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Neural Network Training Acceleration with {PSO} Algorithm on a {GPU}
               Using OpenCL},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {17:1--17:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120910},
  doi       = {10.1145/3120895.3120910},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/LiL17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/MiyajimaKF17,
  author    = {Takaaki Miyajima and
               Kenichi Kubota and
               Naoyuki Fujita},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {A porting and optimization of search for neighbour-particle in {MPS}
               method for {GPU} by using OpenACC},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {12:1--12:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120903},
  doi       = {10.1145/3120895.3120903},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/MiyajimaKF17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/MorishimaOM17,
  author    = {Shin Morishima and
               Masahiro Okazaki and
               Hiroki Matsutani},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {A Case for Remote GPUs over 10GbE Network for {VR} Applications},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {19:1--19:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120914},
  doi       = {10.1145/3120895.3120914},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/MorishimaOM17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/NodaSMFA17,
  author    = {Hiroyuki Noda and
               Ryotaro Sakai and
               Takaaki Miyajima and
               Naoyuki Fujita and
               Hideharu Amano},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Acceleration of the aggregation process in a Hall-thruster simulation
               using Intel {FPGA} {SDK} for OpenCL},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {20:1--20:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120915},
  doi       = {10.1145/3120895.3120915},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/NodaSMFA17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/NouriRGN17,
  author    = {Sajjad Nouri and
               Jens Rettkowski and
               Diana G{\"{o}}hringer and
               Jari Nurmi},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {{HW/SW} Co-design of an {IEEE} 802.11a/g Receiver on Xilinx Zynq SoC
               using High-Level Synthesis},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {15:1--15:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120908},
  doi       = {10.1145/3120895.3120908},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/NouriRGN17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/OrdazK17,
  author    = {Jose Raul Garcia Ordaz and
               Dirk Koch},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {{HLS} Compilation for {CPU} Interlays},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {27:1--27:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120922},
  doi       = {10.1145/3120895.3120922},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/OrdazK17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/OsanaS17,
  author    = {Yasunori Osana and
               Yohei Sakamoto},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Performance Evaluation of a {CPU-FPGA} Hybrid Cluster Platform Prototype},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {22:1--22:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120917},
  doi       = {10.1145/3120895.3120917},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/OsanaS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/SakakibaraNM17,
  author    = {Yuma Sakakibara and
               Kohei Nakamura and
               Hiroki Matsutani},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {An {FPGA} {NIC} Based Hardware Caching for Blockchain},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {1:1--1:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120897},
  doi       = {10.1145/3120895.3120897},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/SakakibaraNM17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/SanoAU17,
  author    = {Kentaro Sano and
               Shin Abiko and
               Tomohiro Ueno},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {FPGA-based Stream Computing for High-Performance N-Body Simulation
               using Floating-Point {DSP} Blocks},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {16:1--16:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120909},
  doi       = {10.1145/3120895.3120909},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/SanoAU17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/ShelorK17,
  author    = {Charles Shelor and
               Krishna M. Kavi},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Dataflow based Near Data Computing Achieves Excellent Energy Efficiency},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {6:1--6:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120900},
  doi       = {10.1145/3120895.3120900},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/ShelorK17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/StamouliasMMSKS17,
  author    = {Ioannis Stamoulias and
               Matthias M{\"{o}}ller and
               Rene Miedema and
               Christos Strydis and
               Christoforos Kachris and
               Dimitrios Soudris},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {High-Performance Hardware Accelerators for Solving Ordinary Differential
               Equations},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {24:1--24:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120919},
  doi       = {10.1145/3120895.3120919},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/StamouliasMMSKS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/SugataOOY17,
  author    = {Yuhei Sugata and
               Takeshi Ohkawa and
               Kanemitsu Ootsu and
               Takashi Yokota},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Acceleration of Publish/Subscribe Messaging in ROS-compliant {FPGA}
               Component},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {13:1--13:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120904},
  doi       = {10.1145/3120895.3120904},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/SugataOOY17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/TadaSE17,
  author    = {Jubee Tada and
               Masayuki Sato and
               Ryusuke Egawa},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {An Adaptive Demotion Policy for High-Associativity Caches},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {4:1--4:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120906},
  doi       = {10.1145/3120895.3120906},
  timestamp = {Fri, 27 Dec 2019 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/TadaSE17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/WijesunderaIPS17,
  author    = {Deshya Wijesundera and
               Achintha Ihalage and
               Alok Prakash and
               Thambipillai Srikanthan},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {High Speed Performance Estimation of Embedded Hard-core Processors
               in FPGA-based SoCs},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {2:1--2:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120902},
  doi       = {10.1145/3120895.3120902},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/WijesunderaIPS17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@inproceedings{DBLP:conf/heart/YamamotoHTIAM17,
  author    = {Kasho Yamamoto and
               Weiqiang Huang and
               Shinya Takamaeda{-}Yamazaki and
               Masayuki Ikebe and
               Tetsuya Asai and
               Masato Motomura},
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {A Time-Division Multiplexing Ising Machine on FPGAs},
  booktitle = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  pages     = {3:1--3:6},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895.3120905},
  doi       = {10.1145/3120895.3120905},
  timestamp = {Tue, 06 Nov 2018 16:57:58 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/YamamotoHTIAM17.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@proceedings{DBLP:conf/heart/2017,
  editor    = {Diana G{\"{o}}hringer and
               Michael H{\"{u}}bner},
  title     = {Proceedings of the 8th International Symposium on Highly Efficient
               Accelerators and Reconfigurable Technologies, {HEART} 2017, Bochum,
               Germany, June 7-9, 2017},
  publisher = {{ACM}},
  year      = {2017},
  url       = {https://doi.org/10.1145/3120895},
  doi       = {10.1145/3120895},
  isbn      = {978-1-4503-5316-8},
  timestamp = {Tue, 06 Nov 2018 00:00:00 +0100},
  biburl    = {https://dblp.org/rec/conf/heart/2017.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/DHollander16,
  author    = {Erik H. D'Hollander},
  title     = {High-Level Synthesis Optimization for Blocked Floating-Point Matrix
               Multiplication},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {74--79},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039916},
  doi       = {10.1145/3039902.3039916},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/DHollander16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/EslamiW16,
  author    = {Fatemeh Eslami and
               Steven J. E. Wilton},
  title     = {An Improved Overlay and Mapping Algorithm Supporting Rapid Triggering
               for {FPGA} Debug},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {20--25},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039907},
  doi       = {10.1145/3039902.3039907},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/EslamiW16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/HoutgastSBA16,
  author    = {Ernst Joachim Houtgast and
               Vlad Mihai Sima and
               Koen Bertels and
               Zaid Al{-}Ars},
  title     = {An Efficient GPUAccelerated Implementation of Genomic Short Read Mapping
               with {BWAMEM}},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {38--43},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039910},
  doi       = {10.1145/3039902.3039910},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/HoutgastSBA16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/KnodelGS16,
  author    = {Oliver Knodel and
               Paul R. Genssler and
               Rainer G. Spallek},
  title     = {Migration of long-running Tasks between Reconfigurable Resources using
               Virtualization},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {56--61},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039913},
  doi       = {10.1145/3039902.3039913},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/KnodelGS16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/KobayashiMK16,
  author    = {Ryohei Kobayashi and
               Tomohiro Misono and
               Kenji Kise},
  title     = {A High-speed Verilog {HDL} Simulation Method using a Lightweight Translator},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {26--31},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039908},
  doi       = {10.1145/3039902.3039908},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/KobayashiMK16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/LiYMY16,
  author    = {Chengzhe Li and
               Lai Yoong Yee and
               Hiroshi Maruyama and
               Yoshiki Yamaguchi},
  title     = {FPGA-based Volleyball Player Tracker},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {80--86},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039917},
  doi       = {10.1145/3039902.3039917},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/LiYMY16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/LinJFSY16,
  author    = {Colin Yu Lin and
               Zhenghong Jiang and
               Cheng Fu and
               Hayden Kwok{-}Hay So and
               Haigang Yang},
  title     = {{FPGA} High-level Synthesis versus Overlay: Comparisons on Computation
               Kernels},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {92--97},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039919},
  doi       = {10.1145/3039902.3039919},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/LinJFSY16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MashimoCK16,
  author    = {Susumu Mashimo and
               Thiem Van Chu and
               Kenji Kise},
  title     = {Cost-Effective and High-Throughput Merge Network: Architecture for
               the Fastest {FPGA} Sorting Accelerator},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {8--13},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039905},
  doi       = {10.1145/3039902.3039905},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MashimoCK16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/NakaharaNIS16,
  author    = {Hiroki Nakahara and
               Hiroyuki Nakanishi and
               Kazumasa Iwai and
               Tsutomu Sasao},
  title     = {An {FFT} Circuit for a Spectrometer of a Radio Telescope using the
               Nested {RNS} including the Constant Division},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {44--49},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039911},
  doi       = {10.1145/3039902.3039911},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/NakaharaNIS16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/PangraciousA16,
  author    = {Vinod Pangracious and
               Mulhim Al{-}Doori},
  title     = {Novel Three-Dimensional Embedded {FPGA} Technology and Achitecture},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {50--55},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039912},
  doi       = {10.1145/3039902.3039912},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/PangraciousA16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Pham-QuocNT16,
  author    = {Cuong Pham{-}Quoc and
               Biet Nguyen and
               Tran Ngoc Thinh},
  title     = {FPGA-based Multicore Architecture for Integrating Multiple DDoS Defense
               Mechanisms},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {14--19},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039906},
  doi       = {10.1145/3039902.3039906},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Pham-QuocNT16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SassaKCY16,
  author    = {Shohei Sassa and
               Kenji Kanazawa and
               Shaowei Cai and
               Moritoshi Yasunaga},
  title     = {An {FPGA} Solver for Partial MaxSAT Problems Based on Stochastic Local
               Search},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {32--37},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039909},
  doi       = {10.1145/3039902.3039909},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SassaKCY16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/ShengXYH16,
  author    = {Jiayi Sheng and
               Qingqing Xiong and
               Chen Yang and
               Martin C. Herbordt},
  title     = {Collective Communication on {FPGA} Clusters with Static Scheduling},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {2--7},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039904},
  doi       = {10.1145/3039902.3039904},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/ShengXYH16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SuLTC16,
  author    = {Jiang Su and
               Jianxiong Liu and
               David B. Thomas and
               Peter Y. K. Cheung},
  title     = {Neural Network Based Reinforcement Learning Acceleration on {FPGA}
               Platforms},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {68--73},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039915},
  doi       = {10.1145/3039902.3039915},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SuLTC16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TadaHEK16,
  author    = {Jubee Tada and
               Maiki Hosokawa and
               Ryusuke Egawa and
               Hiroaki Kobayashi},
  title     = {Effects of Stacking Granularity on 3-D Stacked Floating-point Fused
               Multiply Add Units},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {62--67},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039914},
  doi       = {10.1145/3039902.3039914},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TadaHEK16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/ZhaoAIKS16,
  author    = {Qian Zhao and
               Motoki Amagasaki and
               Masahiro Iida and
               Morihiro Kuga and
               Toshinori Sueyoshi},
  title     = {A Study of Heterogeneous Computing Design Method based on Virtualization
               Technology},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {44},
  number    = {4},
  pages     = {86--91},
  year      = {2016},
  url       = {https://doi.org/10.1145/3039902.3039918},
  doi       = {10.1145/3039902.3039918},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/ZhaoAIKS16.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Al-WattarAG15,
  author    = {Ahmed Al{-}Wattar and
               Shawki Areibi and
               Gary William Grewal},
  title     = {Efficient Mapping and Allocation of Execution Units to Task Graphs
               using an Evolutionary Framework},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {46--51},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927973},
  doi       = {10.1145/2927964.2927973},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Al-WattarAG15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/ChevallerieKK15,
  author    = {David de la Chevallerie and
               Jens Korinth and
               Andreas Koch},
  title     = {ffLink: {A} Lightweight High-Performance Open-Source {PCI} Express
               Gen3 Interface for Reconfigurable Accelerators},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {34--39},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927971},
  doi       = {10.1145/2927964.2927971},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/ChevallerieKK15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/GuoFTFL15,
  author    = {Liucheng Guo and
               Andreea{-}Ingrid Funie and
               David B. Thomas and
               Haohuan Fu and
               Wayne Luk},
  title     = {Parallel Genetic Algorithms on Multiple FPGAs},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {86--93},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927980},
  doi       = {10.1145/2927964.2927980},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/GuoFTFL15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/HayashiTM15,
  author    = {Ami Hayashi and
               Yuta Tokusashi and
               Hiroki Matsutani},
  title     = {A Line Rate Outlier Filtering {FPGA} {NIC} using 10GbE Interface},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {22--27},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927969},
  doi       = {10.1145/2927964.2927969},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/HayashiTM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/HmidCL15,
  author    = {Soukaina N. Hmid and
               Jos{\'{e}} Gabriel F. Coutinho and
               Wayne Luk},
  title     = {A Transfer-Aware Runtime System for Heterogeneous Asynchronous Parallel
               Execution},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {40--45},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927972},
  doi       = {10.1145/2927964.2927972},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/HmidCL15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/JainLFM15,
  author    = {Abhishek Kumar Jain and
               Xiangwei Li and
               Suhaib A. Fahmy and
               Douglas L. Maskell},
  title     = {Adapting the DySER Architecture with {DSP} Blocks as an Overlay for
               the Xilinx Zynq},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {28--33},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927970},
  doi       = {10.1145/2927964.2927970},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/JainLFM15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/LashgarSB15,
  author    = {Ahmad Lashgar and
               Ebad Salehi and
               Amirali Baniasadi},
  title     = {A Case Study in Reverse Engineering GPGPUs: Outstanding Memory Handling
               Resources},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {15--21},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927968},
  doi       = {10.1145/2927964.2927968},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/LashgarSB15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MefenzaEB15,
  author    = {Michael Mefenza and
               Nicolas Edwards and
               Christophe Bobda},
  title     = {Interface Based Memory Synthesis of Image Processing Applications
               in {FPGA}},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {64--69},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927976},
  doi       = {10.1145/2927964.2927976},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MefenzaEB15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MitsuishiSHKA15,
  author    = {Takuji Mitsuishi and
               Jun Suzuki and
               Yuki Hayashi and
               Masaki Kan and
               Hideharu Amano},
  title     = {Breadth First Search on Cost-efficient Multi-GPU Systems},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {58--63},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927975},
  doi       = {10.1145/2927964.2927975},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MitsuishiSHKA15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MomeniTUSK15,
  author    = {Amir Momeni and
               Hamed Tabkhi and
               Yash Ukidave and
               Gunar Schirner and
               David R. Kaeli},
  title     = {Exploring the Efficiency of the OpenCL Pipe Semantic on an {FPGA}},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {52--57},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927974},
  doi       = {10.1145/2927964.2927974},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MomeniTUSK15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/OkinaSFSO15,
  author    = {Koji Okina and
               Rie Soejima and
               Kota Fukumoto and
               Yuichiro Shibata and
               Kiyoshi Oguri},
  title     = {Power Performance Profiling of 3-D Stencil Computation on an {FPGA}
               Accelerator for Efficient Pipeline Optimization},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {9--14},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927967},
  doi       = {10.1145/2927964.2927967},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/OkinaSFSO15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SanoKNVS15,
  author    = {Kentaro Sano and
               Fumiya Kono and
               Naohito Nakasato and
               Alexander Vazhenin and
               Stanislav Sedukhin},
  title     = {Stream Computation of Shallow Water Equation Solver for FPGA-based
               1D Tsunami Simulation},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {82--87},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927979},
  doi       = {10.1145/2927964.2927979},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SanoKNVS15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Thorson15a,
  author    = {Mark Thorson},
  title     = {Internet Nuggets},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {94--100},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927982},
  doi       = {10.1145/2927964.2927982},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Thorson15a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TongP15,
  author    = {Da Tong and
               Viktor K. Prasanna},
  title     = {High Throughput Sketch Based Online Heavy Hitter Detection on {FPGA}},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {70--75},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927977},
  doi       = {10.1145/2927964.2927977},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TongP15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TsurutaMKAU15,
  author    = {Chiharu Tsuruta and
               Yohei Miki and
               Takuya Kuhara and
               Hideharu Amano and
               Masayuki Umemura},
  title     = {Off-Loading {LET} Generation to {PEACH2:} {A} Switching Hub for High
               Performance {GPU} Clusters},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {3--8},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927966},
  doi       = {10.1145/2927964.2927966},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TsurutaMKAU15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/WangJZ15,
  author    = {Xinying Wang and
               Phillip H. Jones and
               Joseph Zambreno},
  title     = {A Configurable Architecture for Sparse {LU} Decomposition on Matrices
               with Arbitrary Patterns},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {43},
  number    = {4},
  pages     = {76--81},
  year      = {2015},
  url       = {https://doi.org/10.1145/2927964.2927978},
  doi       = {10.1145/2927964.2927978},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/WangJZ15.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/AndoOMKTH14,
  author    = {Yuki Ando and
               Masataka Ogawa and
               Yuya Mizoguchi and
               Kouta Kumagai and
               Miaw Torng{-}Der and
               Shinya Honda},
  title     = {A Case Study of {FPGA} Blokus Duo Solver by System-Level Design},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {57--62},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693725},
  doi       = {10.1145/2693714.2693725},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/AndoOMKTH14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Gohringer14,
  author    = {Diana G{\"{o}}hringer},
  title     = {Reconfigurable Multiprocessor Systems: Handling Hydras Heads - {A}
               Survey},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {39--44},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693722},
  doi       = {10.1145/2693714.2693722},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Gohringer14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/JoldesPT14,
  author    = {Mioara Joldes and
               Valentina Popescu and
               Warwick Tucker},
  title     = {Searching for Sinks for the H{\'{e}}non Map using a Multipleprecision
               {GPU} Arithmetic Library},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {63--68},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693726},
  doi       = {10.1145/2693714.2693726},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/JoldesPT14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/KodamaHBS14,
  author    = {Yuetsu Kodama and
               Toshihiro Hanawa and
               Taisuke Boku and
               Mitsuhisa Sato},
  title     = {{PEACH2:} An FPGA-based PCIe network device for Tightly Coupled Accelerators},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {3--8},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693716},
  doi       = {10.1145/2693714.2693716},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/KodamaHBS14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MitsuishiNSHKA14,
  author    = {Takuji Mitsuishi and
               Shimpei Nomura and
               Jun Suzuki and
               Yuki Hayashi and
               Masaki Kan and
               Hideharu Amano},
  title     = {Accelerating Breadth First Search on {GPU-BOX}},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {81--86},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693729},
  doi       = {10.1145/2693714.2693729},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MitsuishiNSHKA14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MorishimaM14,
  author    = {Shin Morishima and
               Hiroki Matsutani},
  title     = {Performance Evaluations of Graph Database using {CUDA} and OpenMP
               Compatible Libraries},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {75--80},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693728},
  doi       = {10.1145/2693714.2693728},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MorishimaM14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/NomuraMSHKA14,
  author    = {Shimpei Nomura and
               Takuji Mitsuishi and
               Jun Suzuki and
               Yuki Hayashi and
               Masaki Kan and
               Hideharu Amano},
  title     = {Performance Analysis of the Multi-GPU System with ExpEther},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {9--14},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693717},
  doi       = {10.1145/2693714.2693717},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/NomuraMSHKA14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Nunez-Yanez14,
  author    = {Jos{\'{e}} L. N{\'{u}}{\~{n}}ez{-}Y{\'{a}}{\~{n}}ez},
  title     = {Energy efficient Reconfigurable Computing with Adaptive Voltage and
               Logic scaling},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {87--92},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693730},
  doi       = {10.1145/2693714.2693730},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Nunez-Yanez14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SanoCUSIY14,
  author    = {Kentaro Sano and
               Ryotaro Chiba and
               Tomoya Ueno and
               Hayato Suzuki and
               Ryo Ito and
               Satoru Yamamoto},
  title     = {FPGA-based Custom Computing Architecture for Large-Scale Fluid Simulation
               with Building Cube Method},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {45--50},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693723},
  doi       = {10.1145/2693714.2693723},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SanoCUSIY14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SoejimaODSO14,
  author    = {Rie Soejima and
               Koji Okina and
               Keisuke Dohi and
               Yuichiro Shibata and
               Kiyoshi Oguri},
  title     = {A Memory Profiling Framework for Stencil Computation on an {FPGA}
               Accelerator with High Level Synthesis},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {69--74},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693727},
  doi       = {10.1145/2693714.2693727},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SoejimaODSO14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TanabeM14,
  author    = {Yu Tanabe and
               Tsutomu Maruyama},
  title     = {Fast and Accurate Optical Flow Estimation using {FPGA}},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {27--32},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693720},
  doi       = {10.1145/2693714.2693720},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TanabeM14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Thorson14a,
  author    = {Mark Thorson},
  title     = {Internet Nuggets},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {93--101},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693732},
  doi       = {10.1145/2693714.2693732},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Thorson14a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Torres-HuitzilN14,
  author    = {C{\'{e}}sar Torres{-}Huitzil and
               Marco Aurelio Nu{\~{n}}o{-}Maganda},
  title     = {Areatime Efficient Implementation of Local Adaptive Image Thresholding
               in Reconfigurable Hardware},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {33--38},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693721},
  doi       = {10.1145/2693714.2693721},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Torres-HuitzilN14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TsuyamaM14,
  author    = {Haruhisa Tsuyama and
               Tsutomu Maruyama},
  title     = {{GPU} and {FPGA} Acceleration of Level Set Method},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {21--25},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693719},
  doi       = {10.1145/2693714.2693719},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TsuyamaM14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/WangSCGWLLC14,
  author    = {Tao Wang and
               Guangyu Sun and
               Jiahua Chen and
               Jian Gong and
               Haoyang Wu and
               Xiaoguang Li and
               Songwu Lu and
               Jason Cong},
  title     = {{GRT:} {A} Reconfigurable {SDR} Platform with High Performance and
               Usability},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {51--56},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693724},
  doi       = {10.1145/2693714.2693724},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/WangSCGWLLC14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/WatanabeN14,
  author    = {Tsuyoshi Watanabe and
               Naohito Nakasato},
  title     = {{GPU} Accelerated Hybrid Tree Algorithm for Collision Less N-body
               Simulations},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {42},
  number    = {4},
  pages     = {15--20},
  year      = {2014},
  url       = {https://doi.org/10.1145/2693714.2693718},
  doi       = {10.1145/2693714.2693718},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/WatanabeN14.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/ChauTWLCCEM13,
  author    = {Thomas C. P. Chau and
               James Stanley Targett and
               Marlon Wijeyasinghe and
               Wayne Luk and
               Peter Y. K. Cheung and
               Benjamin Cope and
               Alison Eele and
               Jan M. Maciejowski},
  title     = {Accelerating sequential Monte Carlo method for real-time air traffic
               management},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {35--40},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641367},
  doi       = {10.1145/2641361.2641367},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/ChauTWLCCEM13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/DinechinIS13,
  author    = {Florent de Dinechin and
               Matei Istoan and
               Guillaume Sergent},
  title     = {Fixed-point trigonometric functions on FPGAs},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {83--88},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641375},
  doi       = {10.1145/2641361.2641375},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/DinechinIS13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/GiefersPF13,
  author    = {Heiner Giefers and
               Christian Plessl and
               Jens F{\"{o}}rstner},
  title     = {Accelerating finite difference time domain simulations with reconfigurable
               dataflow computers},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {65--70},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641372},
  doi       = {10.1145/2641361.2641372},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/GiefersPF13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Godard13,
  author    = {Ivan Godard},
  title     = {The Mill: split-stream encoding},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {1--5},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641363},
  doi       = {10.1145/2641361.2641363},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Godard13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/GuoLVC13,
  author    = {Ce Guo and
               Wayne Luk and
               Ekaterina Vinkovskaya and
               Rama Cont},
  title     = {Customisable pipelined engine for intensity evaluation in multivariate
               hawkes point processes},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {59--64},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641371},
  doi       = {10.1145/2641361.2641371},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/GuoLVC13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/GuoTL13,
  author    = {Liucheng Guo and
               David B. Thomas and
               Wayne Luk},
  title     = {Customisable architectures for the set covering problem},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {101--106},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641378},
  doi       = {10.1145/2641361.2641378},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/GuoTL13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/HongBII13,
  author    = {Chuan Hong and
               Khaled Benkrid and
               Mohd Nazrin Md. Isa and
               Xabier Iturbe},
  title     = {A run-time reconfigurable system for adaptive high performance efficient
               computing},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {113--118},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641380},
  doi       = {10.1145/2641361.2641380},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/HongBII13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MahramH13,
  author    = {Atabak Mahram and
               Martin C. Herbordt},
  title     = {{NCBI} {BLASTP} on the convey {HC1-EX}},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {41--46},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641368},
  doi       = {10.1145/2641361.2641368},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MahramH13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MaitraS13b,
  author    = {Subhashis Maitra and
               Amitabha Sinha},
  title     = {Design and simulation of {MAC} unit using combinational circuit and
               adder},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {25--33},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641365},
  doi       = {10.1145/2641361.2641365},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MaitraS13b.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/OgawaIAKS13,
  author    = {Yuki Ogawa and
               Masahiro Iida and
               Motoki Amagasaki and
               Morihiro Kuga and
               Toshinori Sueyoshi},
  title     = {A reconfigurable Java accelerator with software compatibility for
               embedded systems},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {71--76},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641373},
  doi       = {10.1145/2641361.2641373},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/OgawaIAKS13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/OhkawaUYOB13,
  author    = {Takeshi Ohkawa and
               Daichi Uetake and
               Takashi Yokota and
               Kanemitsu Ootsu and
               Takanobu Baba},
  title     = {Reconfigurable and hardwired {ORB} engine on {FPGA} by Java-to-HDL
               synthesizer for realtime application},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {77--82},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641374},
  doi       = {10.1145/2641361.2641374},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/OhkawaUYOB13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/PlumbridgeWA13,
  author    = {Gary Plumbridge and
               Jack Whitham and
               Neil C. Audsley},
  title     = {Blueshell: a platform for rapid prototyping of multiprocessor NoCs
               and accelerators},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {107--117},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641379},
  doi       = {10.1145/2641361.2641379},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/PlumbridgeWA13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SanoKSCIUKY13,
  author    = {Kentaro Sano and
               Yoshiaki Kono and
               Hayato Suzuki and
               Ryotaro Chiba and
               Ryo Ito and
               Tomohiro Ueno and
               Kyo Koizumi and
               Satoru Yamamoto},
  title     = {Efficient custom computing of fully-streamed lattice boltzmann method
               on tightly-coupled {FPGA} cluster},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {47--52},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641369},
  doi       = {10.1145/2641361.2641369},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SanoKSCIUKY13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Tada13,
  author    = {Jubee Tada},
  title     = {Performance evaluation of 3-D stacked 32-bit parallel multipliers},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {89--94},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641376},
  doi       = {10.1145/2641361.2641376},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Tada13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TanakaSK13,
  author    = {Yuichiro Tanaka and
               Shimpei Sato and
               Kenji Kise},
  title     = {The Ultrasmall soft processor},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {95--100},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641377},
  doi       = {10.1145/2641361.2641377},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TanakaSK13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Thomasian13,
  author    = {Alexander Thomasian},
  title     = {Disk arrays with multiple {RAID} levels},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {6--24},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641364},
  doi       = {10.1145/2641361.2641364},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Thomasian13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Thorson13b,
  author    = {Mark Thorson},
  title     = {Internet nuggets},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {119--127},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641382},
  doi       = {10.1145/2641361.2641382},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Thorson13b.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/VanderbauwhedeFCM13,
  author    = {Wim Vanderbauwhede and
               Anton Frolov and
               Sai Rahul Chalamalasetti and
               Martin Margala},
  title     = {A hybrid {CPU-FPGA} system for high throughput (10Gb/s) streaming
               document classification},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {41},
  number    = {5},
  pages     = {53--58},
  year      = {2013},
  url       = {https://doi.org/10.1145/2641361.2641370},
  doi       = {10.1145/2641361.2641370},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/VanderbauwhedeFCM13.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/ChauLC12,
  author    = {Thomas C. P. Chau and
               Wayne Luk and
               Peter Y. K. Cheung},
  title     = {Roberts: reconfigurable platform for benchmarking real-time systems},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {10--15},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460219},
  doi       = {10.1145/2460216.2460219},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/ChauLC12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/KakimotoDSO12,
  author    = {Takeshi Kakimoto and
               Keisuke Dohi and
               Yuichiro Shibata and
               Kiyoshi Oguri},
  title     = {Performance comparison of {GPU} programming frameworks with the striped
               Smith-Waterman algorithm},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {70--75},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460229},
  doi       = {10.1145/2460216.2460229},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/KakimotoDSO12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/KinoshitaTOYY12,
  author    = {Kei Kinoshita and
               Daisuke Takano and
               Tomoyuki Okamura and
               Tetsuhiko Yao and
               Yoshiki Yamaguchi},
  title     = {An augmented reality system with a coarse-grained reconfigurable device},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {16--21},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460220},
  doi       = {10.1145/2460216.2460220},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/KinoshitaTOYY12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/LinS12,
  author    = {Colin Yu Lin and
               Hayden Kwok{-}Hay So},
  title     = {Energy-efficient dataflow computations on FPGAs using application-specific
               coarse-grain architecture synthesis},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {58--63},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460227},
  doi       = {10.1145/2460216.2460227},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/LinS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/LingBH12,
  author    = {Cheng Ling and
               Khaled Benkrid and
               Tsuyoshi Hamada},
  title     = {High performance phylogenetic analysis on CUDA-compatible GPUs},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {52--57},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460226},
  doi       = {10.1145/2460216.2460226},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/LingBH12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MalikPH12,
  author    = {Jamshaid Sarwar Malik and
               Paolo Palazzari and
               Ahmed Hemani},
  title     = {Effort, resources, and abstraction vs performance in high-level synthesis:
               finding new answers to an old question},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {64--69},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460228},
  doi       = {10.1145/2460216.2460228},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MalikPH12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/NakaharaNS12,
  author    = {Hiroki Nakahara and
               Hiroyuki Nakanishi and
               Tsutomu Sasao},
  title     = {On a wideband fast fourier transform for a radio telescope},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {46--51},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460225},
  doi       = {10.1145/2460216.2460225},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/NakaharaNS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/NakayaMSNS12,
  author    = {Shogo Nakaya and
               Makoto Miyamura and
               Noboru Sakimura and
               Yuichi Nakamura and
               Tadahiko Sugibayashi},
  title     = {A non-volatile reconfigurable offloader for wireless sensor nodes},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {87--92},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460232},
  doi       = {10.1145/2460216.2460232},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/NakayaMSNS12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/NgYNT12,
  author    = {Nicholas Ng and
               Nobuko Yoshida and
               Xinyu Niu and
               Kuen Hung Tsoi},
  title     = {Session types: towards safe and fast reconfigurable programming},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {22--27},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460221},
  doi       = {10.1145/2460216.2460221},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/NgYNT12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SanoK12,
  author    = {Kentaro Sano and
               Yoshiaki Kono},
  title     = {FPGA-based Connect6 solver with hardware-accelerated move refinement},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {4--9},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460218},
  doi       = {10.1145/2460216.2460218},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SanoK12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/ShunM12,
  author    = {Zheng Zhi Shun and
               Tsutomu Maruyama},
  title     = {{FPGA} acceleration of {CDO} pricing based on correlation expansions},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {40--45},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460224},
  doi       = {10.1145/2460216.2460224},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/ShunM12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SyedHV12,
  author    = {Rizwan Syed and
               Yajun Ha and
               Bharadwaj Veeravalli},
  title     = {A low overhead abstract architecture for {FPGA} resource management},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {28--33},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460222},
  doi       = {10.1145/2460216.2460222},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SyedHV12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Thorson12b,
  author    = {Mark Thorson},
  title     = {Internet nuggets},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {93--112},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460234},
  doi       = {10.1145/2460216.2460234},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Thorson12b.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TribinoTCM12,
  author    = {Julien Tribino and
               Antoine Trouv{\'{e}} and
               Hadrien A. Clarke and
               Kazuaki J. Murakami},
  title     = {{PASTIS:} a photonic arbitration with scalable token injection scheme},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {76--81},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460230},
  doi       = {10.1145/2460216.2460230},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TribinoTCM12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TsoiBL12,
  author    = {Kuen Hung Tsoi and
               Tobias Becker and
               Wayne Luk},
  title     = {Modelling reconfigurable systems in event driven simulation},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {34--39},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460223},
  doi       = {10.1145/2460216.2460223},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TsoiBL12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/WatanabeW12,
  author    = {Takahiro Watanabe and
               Minoru Watanabe},
  title     = {0.18 {\(\mu\)}m {CMOS} proess high-sensitivity optially reonfgurable
               gatearray {VLSI}},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {40},
  number    = {5},
  pages     = {82--86},
  year      = {2012},
  url       = {https://doi.org/10.1145/2460216.2460231},
  doi       = {10.1145/2460216.2460231},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/WatanabeW12.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/AgyemanA11,
  author    = {Michael Opoku Agyeman and
               Ali Ahmadinia},
  title     = {Power and area optimisation in heterogeneous 3D networks-on-chip architectures},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {106--107},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082187},
  doi       = {10.1145/2082156.2082187},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/AgyemanA11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/AkagicA11,
  author    = {Amila Akagic and
               Hideharu Amano},
  title     = {High speed {CRC} with 64-bit generator polynomial on an {FPGA}},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {72--77},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082175},
  doi       = {10.1145/2082156.2082175},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/AkagicA11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/AkamineIOFA11,
  author    = {Takayuki Akamine and
               Kenta Inakagata and
               Yasunori Osana and
               Naoyuki Fujita and
               Hideharu Amano},
  title     = {An implementation of out-of-order execution system for acceleration
               of computational fluid dynamics on FPGAs},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {50--55},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082169},
  doi       = {10.1145/2082156.2082169},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/AkamineIOFA11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/BalevicK11,
  author    = {Ana Balevic and
               Bart Kienhuis},
  title     = {{KPN2GPU:} an approach for discovery and exploitation of fine-grain
               data parallelism in process networks},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {66--71},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082173},
  doi       = {10.1145/2082156.2082173},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/BalevicK11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/BonamyCSB11,
  author    = {Robin Bonamy and
               Daniel Chillet and
               Olivier Sentieys and
               S{\'{e}}bastien Bilavarn},
  title     = {Parallelism Level Impact on Energy Consumption in Reconfigurable Devices},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {104--105},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082186},
  doi       = {10.1145/2082156.2082186},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/BonamyCSB11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/ChenYHYS11,
  author    = {Junying Chen and
               Billy Y. S. Yiu and
               Brandon Kyle Hamilton and
               Alfred C. H. Yu and
               Hayden Kwok{-}Hay So},
  title     = {Design space exploration of adaptive beamforming acceleration for
               bedside and portable medical ultrasound imaging},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {20--25},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082162},
  doi       = {10.1145/2082156.2082162},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/ChenYHYS11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/DohiSOF11,
  author    = {Keisuke Dohi and
               Yuichiro Shibata and
               Kiyoshi Oguri and
               Takafumi Fujimoto},
  title     = {{GPU} implementation and optimization of electromagnetic simulation
               using the {FDTD} method for antenna designing},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {26--31},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082163},
  doi       = {10.1145/2082156.2082163},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/DohiSOF11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/FousekFM11,
  author    = {Jan Fousek and
               Jiri Filipovic and
               Matus Madzin},
  title     = {Automatic fusions of {CUDA-GPU} kernels for parallel map},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {98--99},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082183},
  doi       = {10.1145/2082156.2082183},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/FousekFM11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/GeorgescuC11,
  author    = {Serban Georgescu and
               Peter Chow},
  title     = {{GPU} accelerated {CAE} using open solvers and the cloud},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {14--19},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082161},
  doi       = {10.1145/2082156.2082161},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/GeorgescuC11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/KubotaW11,
  author    = {Shinya Kubota and
               Minoru Watanabe},
  title     = {A {MEMS} writer system embedded for a programmable optically reconfigurable
               gate array},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {94--97},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082181},
  doi       = {10.1145/2082156.2082181},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/KubotaW11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/LeeserYBK11,
  author    = {Miriam Leeser and
               Devon Yablonski and
               Dana H. Brooks and
               Laurie A. Smith King},
  title     = {The challenges of writing portable, correct and high performance libraries
               for GPUs},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {2--7},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082158},
  doi       = {10.1145/2082156.2082158},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/LeeserYBK11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/LiuNER11,
  author    = {Haisheng Liu and
               Sma{\"{\i}}l Niar and
               Yassin Elhillali and
               Atika Rivenq},
  title     = {Embedded architecture with hardware accelerator for target recognition
               in driver assistance system},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {56--59},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082170},
  doi       = {10.1145/2082156.2082170},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/LiuNER11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MatsunobuDSO11,
  author    = {Kohei Matsunobu and
               Keisuke Dohi and
               Yuichiro Shibata and
               Kiyoshi Oguri},
  title     = {A discussion on calculating eigenvalues of real symmetric tridiagonal
               matrices on a {GPU}},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {100--101},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082184},
  doi       = {10.1145/2082156.2082184},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MatsunobuDSO11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MeyerK11,
  author    = {Dominik Meyer and
               Bernd Klauer},
  title     = {Multicore reconfiguration platform an alternative to RAMPSoC},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {102--103},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082185},
  doi       = {10.1145/2082156.2082185},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MeyerK11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/NagatsukaSMK11,
  author    = {Tomoyuki Nagatsuka and
               Yoshito Sakaguchi and
               Takayuki Matsumura and
               Kenji Kise},
  title     = {CoreSymphony: an efficient reconfigurable multi-core architecture},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {32--37},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082165},
  doi       = {10.1145/2082156.2082165},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/NagatsukaSMK11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/PellM11,
  author    = {Oliver Pell and
               Oskar Mencer},
  title     = {Surviving the end of frequency scaling with reconfigurable dataflow
               computing},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {60--65},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082172},
  doi       = {10.1145/2082156.2082172},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/PellM11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SanoYH11,
  author    = {Kentaro Sano and
               Satoru Yamamoto and
               Yoshiaki Hatsuda},
  title     = {Domain-specific programmable design of scalable streaming-array for
               power-efficient stencil computation},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {44--49},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082168},
  doi       = {10.1145/2082156.2082168},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SanoYH11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SawadaKAIS11,
  author    = {Hiroomi Sawada and
               Morihiro Kuga and
               Motoki Amagasaki and
               Masahiro Iida and
               Toshinori Sueyoshi},
  title     = {Parallelization of the channel width search for {FPGA} routing},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {82--85},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082177},
  doi       = {10.1145/2082156.2082177},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SawadaKAIS11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Takamaeda-YamazakiSSK11,
  author    = {Shinya Takamaeda{-}Yamazaki and
               Ryosuke Sasakawa and
               Yoshito Sakaguchi and
               Kenji Kise},
  title     = {An FPGA-based scalable simulation accelerator for tile architectures},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {38--43},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082166},
  doi       = {10.1145/2082156.2082166},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Takamaeda-YamazakiSSK11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TanabeNY11,
  author    = {Shoji Tanabe and
               Takuya Nagashima and
               Yoshiki Yamaguchi},
  title     = {A study of an {FPGA} based flexible {SIMD} processor},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {86--89},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082179},
  doi       = {10.1145/2082156.2082179},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TanabeNY11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Thorson11a,
  author    = {Mark Thorson},
  title     = {Internet nuggets},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {108--117},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082189},
  doi       = {10.1145/2082156.2082189},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Thorson11a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TrouveM11,
  author    = {Antoine Trouv{\'{e}} and
               Kazuaki J. Murakami},
  title     = {Augmenting {DR-ASIP} flexibility through multi-mode custom instructions},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {90--93},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082180},
  doi       = {10.1145/2082156.2082180},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TrouveM11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TsoiL11,
  author    = {Kuen Hung Tsoi and
               Wayne Luk},
  title     = {Power profiling and optimization for heterogeneous multi-core systems},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {8--13},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082159},
  doi       = {10.1145/2082156.2082159},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TsoiL11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/YangM11,
  author    = {Shufan Yang and
               T. Martin McGinnity},
  title     = {A biologically plausible real-time spiking neuron simulation environment
               based on a multiple-FPGA platform},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {39},
  number    = {4},
  pages     = {78--81},
  year      = {2011},
  url       = {https://doi.org/10.1145/2082156.2082176},
  doi       = {10.1145/2082156.2082176},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/YangM11.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/BanescuDPT10,
  author    = {Sebastian Banescu and
               Florent de Dinechin and
               Bogdan Pasca and
               Radu Tudoran},
  title     = {Multipliers for floating-point double precision and beyond on FPGAs},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {73--79},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926380},
  doi       = {10.1145/1926367.1926380},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/BanescuDPT10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/DohiSHMOB10,
  author    = {Keisuke Dohi and
               Yuichiro Shibata and
               Tsuyoshi Hamada and
               Tomonari Masada and
               Kiyoshi Oguri and
               Duncan A. Buell},
  title     = {Implementation of a programming environment with a multithread model
               for reconfigurable systems},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {40--45},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926375},
  doi       = {10.1145/1926367.1926375},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/DohiSHMOB10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/HoritaT10,
  author    = {Tadayoshi Horita and
               Itsuo Takanami},
  title     = {An FPGA-based fast classifier with high generalization property},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {21--26},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926372},
  doi       = {10.1145/1926367.1926372},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/HoritaT10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/MorishitaIOFA10,
  author    = {Hirokazu Morishita and
               Kenta Inakagata and
               Yasunori Osana and
               Naoyuki Fujita and
               Hideharu Amano},
  title     = {Implementation and evaluation of an arithmetic pipeline on {FLOPS-2D:}
               multi-FPGA system},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {8--13},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926370},
  doi       = {10.1145/1926367.1926370},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/MorishitaIOFA10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Nuno-MagandaT10,
  author    = {Marco Aurelio Nu{\~{n}}o{-}Maganda and
               C{\'{e}}sar Torres{-}Huitzil},
  title     = {A temporal coding hardware implementation for spiking neural networks},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {2--7},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926369},
  doi       = {10.1145/1926367.1926369},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Nuno-MagandaT10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/PaekCL10,
  author    = {Jong Kyung Paek and
               Kiyoung Choi and
               Jong{-}eun Lee},
  title     = {Binary acceleration using coarse-grained reconfigurable architecture},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {33--39},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926374},
  doi       = {10.1145/1926367.1926374},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/PaekCL10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/PutnamSB10,
  author    = {Andrew Putnam and
               Aaron Smith and
               Doug Burger},
  title     = {Dynamic vectorization in the {E2} dynamic multicore architecture},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {27--32},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926373},
  doi       = {10.1145/1926367.1926373},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/PutnamSB10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SabeghiMB10,
  author    = {Mojtaba Sabeghi and
               Hamid Mushtaq and
               Koen Bertels},
  title     = {Runtime multitasking support on polymorphic platforms},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {46--52},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926376},
  doi       = {10.1145/1926367.1926376},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SabeghiMB10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/SanoWY10,
  author    = {Kentaro Sano and
               Luzhou Wang and
               Satoru Yamamoto},
  title     = {Prototype implementation of array-processor extensible over multiple
               FPGAs for scalable stencil computation},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {80--86},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926381},
  doi       = {10.1145/1926367.1926381},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/SanoWY10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TadonkiGP10,
  author    = {Claude Tadonki and
               Gilbert Grosdidier and
               Olivier P{\`{e}}ne},
  title     = {An efficient {CELL} library for lattice quantum chromodynamics},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {60--65},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926378},
  doi       = {10.1145/1926367.1926378},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TadonkiGP10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TaylorL10,
  author    = {Ryan Taylor and
               Xiaoming Li},
  title     = {Software-based branch predication for {AMD} GPUs},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {66--72},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926379},
  doi       = {10.1145/1926367.1926379},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TaylorL10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/Thorson10a,
  author    = {Mark Thorson},
  title     = {Internet nuggets},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {93--96},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926384},
  doi       = {10.1145/1926367.1926384},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/Thorson10a.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TsangS10,
  author    = {Chi Chiu Tsang and
               Hayden Kwok{-}Hay So},
  title     = {Dynamic power reduction of FPGA-based reconfigurable computers using
               precomputation},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {87--92},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926382},
  doi       = {10.1145/1926367.1926382},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TsangS10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TseTTL10,
  author    = {Anson H. T. Tse and
               David B. Thomas and
               Kuen Hung Tsoi and
               Wayne Luk},
  title     = {Efficient reconfigurable design for pricing asian options},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {14--20},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926371},
  doi       = {10.1145/1926367.1926371},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TseTTL10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
@article{DBLP:journals/sigarch/TsoiTPL10,
  author    = {Kuen Hung Tsoi and
               Anson H. T. Tse and
               Peter R. Pietzuch and
               Wayne Luk},
  title     = {Programming framework for clusters with heterogeneous accelerators},
  journal   = {{SIGARCH} Comput. Archit. News},
  volume    = {38},
  number    = {4},
  pages     = {53--59},
  year      = {2010},
  url       = {https://doi.org/10.1145/1926367.1926377},
  doi       = {10.1145/1926367.1926377},
  timestamp = {Thu, 30 Jul 2020 01:00:00 +0200},
  biburl    = {https://dblp.org/rec/journals/sigarch/TsoiTPL10.bib},
  bibsource = {dblp computer science bibliography, https://dblp.org}
}
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