:facetid:toc:\"db/conf/dft/dft2000.bht\"OK:facetid:toc:db/conf/dft/dft2000.bhtMonica AlderighiSergio D'AngeloGiacomo R. SechiCecilia MetraAchieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs.DFT155-1632000Conference and Workshop Papersclosedconf/dft/AlderighiDSM0010.1109/DFTVS.2000.887153https://doi.org/10.1109/DFTVS.2000.887153https://dblp.org/rec/conf/dft/AlderighiDSM00URL#6445148Lörinc AntoniRégis LeveugleBéla FehérUsing Run-Time Reconfiguration for Fault Injection in Hardware Prototypes.DFT405-4132000Conference and Workshop Papersclosedconf/dft/AntoniLF0010.1109/DFTVS.2000.887181https://doi.org/10.1109/DFTVS.2000.887181https://dblp.org/rec/conf/dft/AntoniLF00URL#6445149Andrea BaldiniAlfredo BensoSilvia ChiusanoPaolo Prinetto'BOND': An Interposition Agents Based Fault Injector for Windows NT.DFT387-3952000Conference and Workshop Papersclosedconf/dft/BaldiniBCP0010.1109/DFTVS.2000.887179https://doi.org/10.1109/DFTVS.2000.887179https://dblp.org/rec/conf/dft/BaldiniBCP00URL#6445150Juan Carlos BarazaJoaquin GraciaDaniel GilPedro J. GilA Prototype of a VHDL-Based Fault Injection Tool.DFT396-4042000Conference and Workshop Papersclosedconf/dft/BarazaGGG0010.1109/DFTVS.2000.887180https://doi.org/10.1109/DFTVS.2000.887180https://dblp.org/rec/conf/dft/BarazaGGG00URL#6445151Alfredo BensoSilvia ChiusanoPaolo PrinettoP. SimonottiG. UgoSelf-Repairing in a Micro-Programmed Processor for Dependable Applications.DFT231-2392000Conference and Workshop Papersclosedconf/dft/BensoCPSU0010.1109/DFTVS.2000.887161https://doi.org/10.1109/DFTVS.2000.887161https://dblp.org/rec/conf/dft/BensoCPSU00URL#6445152Giuseppe BiasoliFabrizio FerrandiDonatella SciutoAlessandro FinFranco FummiBIST Architectures Selection Based on Behavioral Testing.DFT292-2982000Conference and Workshop Papersclosedconf/dft/BiasoliFSFF0010.1109/DFTVS.2000.887169https://doi.org/10.1109/DFTVS.2000.887169https://dblp.org/rec/conf/dft/BiasoliFSFF00URL#6445153Gian Carlo CardarilliAdelio SalsanoP. MarinucciMarco OttaviA Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture.DFT173-2000Conference and Workshop Papersclosedconf/dft/CardarilliSMO0010.1109/DFTVS.2000.887155https://doi.org/10.1109/DFTVS.2000.887155https://dblp.org/rec/conf/dft/CardarilliSMO00URL#6445154Chuang ChengChih-Tsun HuangJing-Reng HuangCheng-Wen WuChen-Jong WeyMing-Chang TsaiBRAINS: A BIST Compiler for Embedded Memories.DFT299-2000Conference and Workshop Papersclosedconf/dft/ChengHHWWT0010.1109/DFTVS.2000.887170https://doi.org/10.1109/DFTVS.2000.887170https://dblp.org/rec/conf/dft/ChengHHWWT00URL#6445155Ching-Hwa ChengJinn-Shyan WangShih-Chieh ChangWen-Ben JoneLow-Speed Scan Testing of Charge-Sharing Faults for CMOS Domino Circuits.DFT329-3372000Conference and Workshop Papersclosedconf/dft/ChengWCJ0010.1109/DFTVS.2000.887173https://doi.org/10.1109/DFTVS.2000.887173https://dblp.org/rec/conf/dft/ChengWCJ00URL#6445156Serge N. DemidenkoEugene M. LevineVincenzo PiuriSynthesis of On-Line Testing Control Units: Flow Graph Coding/Monitoring Approach.DFT266-2742000Conference and Workshop Papersclosedconf/dft/DemidenkoLP0010.1109/DFTVS.2000.887166https://doi.org/10.1109/DFTVS.2000.887166https://dblp.org/rec/conf/dft/DemidenkoLP00URL#6445157Abderrahim DoumarHideo ItoDesign of Switching Blocks Tolerating Defects/Faults in FPGA Interconnection Resources.DFT134-1422000Conference and Workshop Papersclosedconf/dft/DoumarI0010.1109/DFTVS.2000.887151https://doi.org/10.1109/DFTVS.2000.887151https://dblp.org/rec/conf/dft/DoumarI00URL#6445158Masaru FukushiSusumu HoriguchiSelf-Reconfigurable Mesh Array System on FPGA.DFT240-2000Conference and Workshop Papersclosedconf/dft/FukushiH0010.1109/DFTVS.2000.887162https://doi.org/10.1109/DFTVS.2000.887162https://dblp.org/rec/conf/dft/FukushiH00URL#6445159Masaki HashizumeHiroyuki YotsuyanagiTakeomi TamesadaMasashi TakedaTestability Analysis of IDDQ Testing with Large Threshold Value.DFT367-3752000Conference and Workshop Papersclosedconf/dft/HashizumeYTT0010.1109/DFTVS.2000.887177https://doi.org/10.1109/DFTVS.2000.887177https://dblp.org/rec/conf/dft/HashizumeYTT00URL#6445160Klaus Herrmann 0002Sören MochJörg HilgenstockPeter PirschImplementation of a Multiprocessor System with Distributed Embedded DRAM on a Large Area Integrated Circuit.DFT105-1132000Conference and Workshop Papersclosedconf/dft/HerrmannMHP0010.1109/DFTVS.2000.887148https://doi.org/10.1109/DFTVS.2000.887148https://dblp.org/rec/conf/dft/HerrmannMHP00URL#6445161Gert JervanZebo PengRaimund UbarTest Cost Minimization for Hybrid Bist.DFT283-2912000Conference and Workshop Papersclosedconf/dft/JervanPU0010.1109/DFTVS.2000.887168https://doi.org/10.1109/DFTVS.2000.887168https://dblp.org/rec/conf/dft/JervanPU00URL#6445162Xiaohong Jiang 0001Susumu HoriguchiOptimization of Wafer Scale H-Tree Clock Distribution Network Based on a New Statistical Skew Model.DFT96-1042000Conference and Workshop Papersclosedconf/dft/JiangH0010.1109/DFTVS.2000.887147https://doi.org/10.1109/DFTVS.2000.887147https://dblp.org/rec/conf/dft/JiangH00URL#6445163Xiaohong Jiang 0001Susumu HoriguchiYue HaoPredicting the Yield Efficacy of a Defect-Tolerant Embedded Core.DFT30-2000Conference and Workshop Papersclosedconf/dft/JiangHH0010.1109/DFTVS.2000.886971https://doi.org/10.1109/DFTVS.2000.886971https://dblp.org/rec/conf/dft/JiangHH00URL#6445164Naotake KamiuraTakashi KoderaNobuyuki MatsuiDesign of a Fault Tolerant Multistage Interconnection Network with Parallel Duplicated Switches.DFT143-2000Conference and Workshop Papersclosedconf/dft/KamiuraKM0010.1109/DFTVS.2000.887152https://doi.org/10.1109/DFTVS.2000.887152https://dblp.org/rec/conf/dft/KamiuraKM00URL#6445165Yasunao KatayamaYasushi NegishiSumio MoriokaEfficient Error Correction Code Configurations for Quasi-Nonvolatile Data Retention by DRAMs.DFT201-2000Conference and Workshop Papersclosedconf/dft/KatayamaNM0010.1109/DFTVS.2000.887158https://doi.org/10.1109/DFTVS.2000.887158https://dblp.org/rec/conf/dft/KatayamaNM00URL#6445166Madhuban KishorJosé Pineda de GyvezThreshold Voltage and Power-Supply Tolerance of CMOS Logic Design Families.DFT349-3572000Conference and Workshop Papersclosedconf/dft/KishorG0010.1109/DFTVS.2000.887175https://doi.org/10.1109/DFTVS.2000.887175https://dblp.org/rec/conf/dft/KishorG00URL#6445167Masato KitakamiHongyuan ChenEiji FujiwaraEvaluations of Burst Error Recovery for VF Arithmetic Coding.DFT183-1912000Conference and Workshop Papersclosedconf/dft/KitakamiCF0010.1109/DFTVS.2000.887156https://doi.org/10.1109/DFTVS.2000.887156https://dblp.org/rec/conf/dft/KitakamiCF00URL#6445168Israel KorenZahava KorenGlenn H. ChapmanA Self-Correcting Active Pixel Camera.DFT56-2000Conference and Workshop Papersclosedconf/dft/KorenKC0010.1109/DFTVS.2000.886974https://doi.org/10.1109/DFTVS.2000.886974https://dblp.org/rec/conf/dft/KorenKC00URL#6445169Jae-Hyuck KwakEarl E. Swartzlander Jr.Vincenzo PiuriFault-Tolerant High-Performance Cordic Processors.DFT164-1722000Conference and Workshop Papersclosedconf/dft/KwakSP0010.1109/DFTVS.2000.887154https://doi.org/10.1109/DFTVS.2000.887154https://dblp.org/rec/conf/dft/KwakSP00URL#6445170Parag K. LalaAlvernon WalkerAn On-Line Reconfigurable FPGA Architecture.DFT275-2000Conference and Workshop Papersclosedconf/dft/LalaW0010.1109/DFTVS.2000.887167https://doi.org/10.1109/DFTVS.2000.887167https://dblp.org/rec/conf/dft/LalaW00URL#6445171R. M. LeaP. T. TetnowskiM. CovicA Reconfigurable WSI Massively Data-Parallel Processing Device for Cost-Effective 3D Sensor Data Processing.DFT87-952000Conference and Workshop Papersclosedconf/dft/LeaTC0010.1109/DFTVS.2000.887146https://doi.org/10.1109/DFTVS.2000.887146https://dblp.org/rec/conf/dft/LeaTC00URL#6445172Régis LeveugleFault Injection in VHDL Descriptions and Emulation.DFT414-2000Conference and Workshop Papersclosedconf/dft/Leveugle0010.1109/DFTVS.2000.887182https://doi.org/10.1109/DFTVS.2000.887182https://dblp.org/rec/conf/dft/Leveugle00URL#6445173Shengli LiKai ZhangJien-Chung LoThe 2nd Order Analysis of IDDQ Test Data.DFT376-2000Conference and Workshop Papersclosedconf/dft/LiZL0010.1109/DFTVS.2000.887178https://doi.org/10.1109/DFTVS.2000.887178https://dblp.org/rec/conf/dft/LiZL00URL#6445174Ole MendeMichael RedekerMarkus RudackDieter TreytnarA Multifunctional Laser Linking and Cutting Structure for Standard 0.25 mum CMOS-Technology.DFT114-2000Conference and Workshop Papersclosedconf/dft/MendeRRT0010.1109/DFTVS.2000.887149https://doi.org/10.1109/DFTVS.2000.887149https://dblp.org/rec/conf/dft/MendeRRT00URL#6445175Mike MoranGerard A. AllanIC Critical Volume Calculation through Ray-Casting of CSG Trees.DFT12-292000Conference and Workshop Papersclosedconf/dft/MoranA0010.1109/DFTVS.2000.886969https://doi.org/10.1109/DFTVS.2000.886969https://dblp.org/rec/conf/dft/MoranA00URL#6445176Sukalyan MukherjeeDesign for Testability to Achieve High Test Coverage - A Case Study.DFT320-3282000Conference and Workshop Papersclosedconf/dft/Mukherjee0010.1109/DFTVS.2000.887172https://doi.org/10.1109/DFTVS.2000.887172https://dblp.org/rec/conf/dft/Mukherjee00URL#6445177Shigeru OhnishiMichinori NishiharaA New Light-Based Logic IC Screening Method.DFT358-3662000Conference and Workshop Papersclosedconf/dft/OhnishiN0010.1109/DFTVS.2000.887176https://doi.org/10.1109/DFTVS.2000.887176https://dblp.org/rec/conf/dft/OhnishiN00URL#6445178Nohpill ParkFred J. MeyerFabrizio LombardiQuality-Effective Repair of Multichip Module Systems.DFT47-552000Conference and Workshop Papersclosedconf/dft/ParkML0010.1109/DFTVS.2000.886973https://doi.org/10.1109/DFTVS.2000.886973https://dblp.org/rec/conf/dft/ParkML00URL#6445179Nohpill ParkS. J. RuiwaleFabrizio LombardiTesting the Configurability of Dynamic FPGAs.DFT311-3192000Conference and Workshop Papersclosedconf/dft/ParkRL0010.1109/DFTVS.2000.887171https://doi.org/10.1109/DFTVS.2000.887171https://dblp.org/rec/conf/dft/ParkRL00URL#6445180Rajnish K. PrasadIsrael KorenThe Effect of Placement on Yield for Standard Cell Designs.DFT3-112000Conference and Workshop Papersclosedconf/dft/PrasadK0010.1109/DFTVS.2000.886968https://doi.org/10.1109/DFTVS.2000.886968https://dblp.org/rec/conf/dft/PrasadK00URL#6445181Maurizio RebaudengoMatteo Sonza ReordaMarco TorchianoMassimo ViolanteAn Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications.DFT257-2652000Conference and Workshop Papersclosedconf/dft/RebaudengoRTV0010.1109/DFTVS.2000.887164https://doi.org/10.1109/DFTVS.2000.887164https://dblp.org/rec/conf/dft/RebaudengoRTV00URL#6445182Markus RudackMichael RedekerDieter TreytnarOle MendeKlaus Herrmann 0002Self-Configuration of a Large Area Integrated Multiprocessor System for Video Applications.DFT78-862000Conference and Workshop Papersclosedconf/dft/RudackRTMH0010.1109/DFTVS.2000.887145https://doi.org/10.1109/DFTVS.2000.887145https://dblp.org/rec/conf/dft/RudackRTMH00URL#6445183W. ShiK. KumarFabrizio LombardiOn the Complexity of Switch Programming in Fault-Tolerant-Configurable Chips.DFT125-1342000Conference and Workshop Papersclosedconf/dft/ShiKL0010.1109/DFTVS.2000.887150https://doi.org/10.1109/DFTVS.2000.887150https://dblp.org/rec/conf/dft/ShiKL00URL#6445184Janusz SosnowskiTomasz WabiaTomasz BechPath Delay Fault Testability Analysis.DFT338-2000Conference and Workshop Papersclosedconf/dft/SosnowskiWB0010.1109/DFTVS.2000.887174https://doi.org/10.1109/DFTVS.2000.887174https://dblp.org/rec/conf/dft/SosnowskiWB00URL#6445185Andreas SteiningerChristoph ScherrerHow Does Resource Utilization Affect Fault Tolerance?DFT251-2562000Conference and Workshop Papersclosedconf/dft/SteiningerS0010.1109/DFTVS.2000.887163https://doi.org/10.1109/DFTVS.2000.887163https://dblp.org/rec/conf/dft/SteiningerS00URL#6445186Itsuo TakanamiBuilt-in Self-Reconfiguring Systems for Mesh-Connected Processor Arrays with Spares on Two Rows/Columns.DFT213-2212000Conference and Workshop Papersclosedconf/dft/Takanami0010.1109/DFTVS.2000.887159https://doi.org/10.1109/DFTVS.2000.887159https://dblp.org/rec/conf/dft/Takanami00URL#6445187Nobuo TsudaFault-Tolerant Ring- and Toroidal Mesh-Connected Processor Arrays Able to Enhance Emulation of Hypercubes.DFT222-2302000Conference and Workshop Papersclosedconf/dft/Tsuda0010.1109/DFTVS.2000.887160https://doi.org/10.1109/DFTVS.2000.887160https://dblp.org/rec/conf/dft/Tsuda00URL#6445188Ganesan UmanesanEiji FujiwaraSingle Byte Error Control Codes with Double Bit within a Block Error Correcting Capability for Semiconductor Memory Systems.DFT192-2002000Conference and Workshop Papersclosedconf/dft/UmanesanF0010.1109/DFTVS.2000.887157https://doi.org/10.1109/DFTVS.2000.887157https://dblp.org/rec/conf/dft/UmanesanF00URL#6445189Moritoshi YasunagaIkuo YoshiharaJung Hwan KimA High Speed and High Fault Tolerant Reconfigurable Reasoning System: Toward a Wafer Scale Reconfigurable Reasoning LSI.DFT69-772000Conference and Workshop Papersclosedconf/dft/YasunagaYK0010.1109/DFTVS.2000.887144https://doi.org/10.1109/DFTVS.2000.887144https://dblp.org/rec/conf/dft/YasunagaYK00URL#6445190Tianxu ZhaoYue HaoYong-Chang JiaoVLSI Yield Optimization Based on the Sub-Processing-Element Level Redundancy.DFT41-462000Conference and Workshop Papersclosedconf/dft/ZhaoHJ0010.1109/DFTVS.2000.886972https://doi.org/10.1109/DFTVS.2000.886972https://dblp.org/rec/conf/dft/ZhaoHJ00URL#644519115th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 25-27 October 2000, Yamanashi, Japan, ProceedingsDFTIEEE Computer Society2000Editorshipconf/dft/2000https://ieeexplore.ieee.org/xpl/conhome/7115/proceedinghttps://dblp.org/rec/conf/dft/2000URL#6479121