:facetid:toc:\"db/conf/date/date2001.bht\"OK:facetid:toc:db/conf/date/date2001.bhtAndrea AcquavivaLuca BeniniBruno RiccòAn adaptive algorithm for low-power streaming multimedia processing.DATE273-2792001Conference and Workshop Papersclosedconf/date/AcquavivaBR0110.1109/DATE.2001.915037https://doi.org/10.1109/DATE.2001.915037https://dblp.org/rec/conf/date/AcquavivaBR01URL#6360970Bilge Saglam AkgulVincent John Mooney IIISystem-on-a-chip processor synchronization support in hardware.DATE633-6412001Conference and Workshop Papersclosedconf/date/AkgulM0110.1109/DATE.2001.915090https://doi.org/10.1109/DATE.2001.915090https://dblp.org/rec/conf/date/AkgulM01URL#6360971Zaid Al-ArsAd J. van de GoorStatic and dynamic behavior of memory cell array opens and shorts in embedded DRAMs.DATE496-5032001Conference and Workshop Papersclosedconf/date/Al-ArsG0110.1109/DATE.2001.915069https://doi.org/10.1109/DATE.2001.915069https://dblp.org/rec/conf/date/Al-ArsG01URL#6360972Jakob AxelssonMethods and tools for systems engineering of automotive electronic architectures.DATE1122001Conference and Workshop Papersclosedconf/date/Axelsson01https://dl.acm.org/citation.cfm?id=367109https://dblp.org/rec/conf/date/Axelsson01URL#6360973Florence AzaïsSerge BernardYves BertrandMichel RenovellImplementation of a linear histogram BIST for ADCs.DATE590-5952001Conference and Workshop Papersclosedconf/date/AzaisBBR0110.1109/DATE.2001.915083https://doi.org/10.1109/DATE.2001.915083https://dblp.org/rec/conf/date/AzaisBBR01URL#6360974Mustafa BadarogluMarc van HeijningenVincent GravotStéphane DonnayHugo De ManGeorges G. E. GielenMarc EngelsIvo BolsensHigh-level simulation of substrate noise generation from large digital circuits with multiple supplies.DATE326-3302001Conference and Workshop Papersclosedconf/date/BadarogluHGDMGEB0110.1109/DATE.2001.915044https://doi.org/10.1109/DATE.2001.915044https://dblp.org/rec/conf/date/BadarogluHGDMGEB01URL#6360975Amer BaghdadiDamien LyonnardNacer-Eddine ZergainohAhmed Amine JerrayaAn efficient architecture model for systematic design of application-specific multiprocessor SoC.DATE55-632001Conference and Workshop Papersclosedconf/date/BaghdadiLZJ0110.1109/DATE.2001.915001https://doi.org/10.1109/DATE.2001.915001https://dblp.org/rec/conf/date/BaghdadiLZJ01URL#6360976Ismet BayraktarogluAlex OrailogluDiagnosis for scan-based BIST: reaching deep into the signatures.DATE102-1112001Conference and Workshop Papersclosedconf/date/BayraktarogluO0110.1109/DATE.2001.915008https://doi.org/10.1109/DATE.2001.915008https://dblp.org/rec/conf/date/BayraktarogluO01URL#6360977Pirouz Bazargan-SabetFabrice IlponseModeling crosstalk noise for deep submicron verification tools.DATE530-5342001Conference and Workshop Papersclosedconf/date/Bazargan-SabetI0110.1109/DATE.2001.915074https://doi.org/10.1109/DATE.2001.915074https://dblp.org/rec/conf/date/Bazargan-SabetI01URL#6360978Michael W. BeattieLawrence T. PileggiEfficient inductance extraction via windowing.DATE430-4362001Conference and Workshop Papersclosedconf/date/BeattieP0110.1109/DATE.2001.915059https://doi.org/10.1109/DATE.2001.915059https://dblp.org/rec/conf/date/BeattieP01URL#6360979Marco BekooijLoek J. M. EngelsAlbert van der WerfNatalino G. BusáFunctional units with conditional input/output behavior in VLIW processors.DATE8222001Conference and Workshop Papersclosedconf/date/BekooijEWB0110.1109/DATE.2001.915171https://doi.org/10.1109/DATE.2001.915171https://dblp.org/rec/conf/date/BekooijEWB01URL#6360980Mounir BenabdenbiWalid MaroufiMeryem MarzoukiTesting TAPed cores and wrapped cores with the same test access mechanism.DATE150-1552001Conference and Workshop Papersclosedconf/date/BenabdenbiMM0110.1109/DATE.2001.915016https://doi.org/10.1109/DATE.2001.915016https://dblp.org/rec/conf/date/BenabdenbiMM01URL#6360981Luca BeniniGiuliano CastelliAlberto MaciiEnrico MaciiMassimo PoncinoRiccardo ScarsiExtending lifetime of portable systems by battery scheduling.DATE197-2032001Conference and Workshop Papersclosedconf/date/BeniniCMMPS0110.1109/DATE.2001.915024https://doi.org/10.1109/DATE.2001.915024https://dblp.org/rec/conf/date/BeniniCMMPS01URL#6360982Alfredo BensoStefano Di CarloGiorgio Di NatalePaolo PrinettoSEU effect analysis in an open-source router via a distributed fault injection environment.DATE219-2252001Conference and Workshop Papersclosedconf/date/BensoCNP0110.1109/DATE.2001.915028https://doi.org/10.1109/DATE.2001.915028https://dblp.org/rec/conf/date/BensoCNP01URL#6360983Guido BertoniLuca BreveglieriPasqualina FragnetoEfficient finite field digital-serial multiplier architecture for cryptography applications.DATE8122001Conference and Workshop Papersclosedconf/date/BertoniBF0110.1109/DATE.2001.915150https://doi.org/10.1109/DATE.2001.915150https://dblp.org/rec/conf/date/BertoniBF01URL#6360984Bernhard BurdiekGeneration of optimum test stimuli for nonlinear analog circuits using nonlinear - programming and time-domain sensitivities.DATE603-6092001Conference and Workshop Papersclosedconf/date/Burdiek0110.1109/DATE.2001.915085https://doi.org/10.1109/DATE.2001.915085https://dblp.org/rec/conf/date/Burdiek01URL#6360985Gianpiero CabodiPaolo CamuratiStefano QuerBiasing symbolic search by means of dynamic activity profiles.DATE9-152001Conference and Workshop Papersclosedconf/date/CabodiCQ0110.1109/DATE.2001.914993https://doi.org/10.1109/DATE.2001.914993https://dblp.org/rec/conf/date/CabodiCQ01URL#6360986Gregorio CappuccinoGiuseppe CocorulloCMOS sizing rule for high performance long interconnects.DATE8172001Conference and Workshop Papersclosedconf/date/CappuccinoC0110.1109/DATE.2001.915165https://doi.org/10.1109/DATE.2001.915165https://dblp.org/rec/conf/date/CappuccinoC01URL#6360987Albert E. CasavantAarti GuptaS. LiuAkira MukaiyamaKazutoshi WakabayashiPranav AsharProperty-specific witness graph generation for guided simulation.DATE7992001Conference and Workshop Papersclosedconf/date/CasavantGLMWA0110.1109/DATE.2001.915124https://doi.org/10.1109/DATE.2001.915124https://dblp.org/rec/conf/date/CasavantGLMWA01URL#6360988Rafael Castro-LópezFrancisco V. Fernández 0001Manuel Delgado-RestitutoÁngel Rodríguez-VázquezRetargeting of mixed-signal blocks for SoCs.DATE772-7752001Conference and Workshop Papersclosedconf/date/Castro-LopezFDR0110.1109/DATE.2001.915118https://doi.org/10.1109/DATE.2001.915118https://dblp.org/rec/conf/date/Castro-LopezFDR01URL#6360989Anshuman ChandraKrishnendu ChakrabartyEfficient test data compression and decompression for system-on-a-chip using internal scan chains and Golomb coding.DATE145-1492001Conference and Workshop Papersclosedconf/date/ChandraC0110.1109/DATE.2001.915015https://doi.org/10.1109/DATE.2001.915015https://dblp.org/rec/conf/date/ChandraC01URL#6360990Chih-Wei Jim ChangBo Hu 0006Malgorzata Marek-SadowskaIn-place delay constrained power optimization using functional symmetries.DATE377-3822001Conference and Workshop Papersclosedconf/date/ChangHM0110.1109/DATE.2001.915052https://doi.org/10.1109/DATE.2001.915052https://dblp.org/rec/conf/date/ChangHM01URL#6360991Luc CharestMichel ReidEl Mostapha AboulhamidGuy BoisA methodology for interfacing open source systemC with a third party software.DATE162001Conference and Workshop Papersclosedconf/date/CharestRAB0110.1109/DATE.2001.914994https://doi.org/10.1109/DATE.2001.914994https://dblp.org/rec/conf/date/CharestRAB01URL#6360992Tom Chen 0001On the impact of on-chip inductance on signal nets under the influence of power grid noise.DATE451-4592001Conference and Workshop Papersclosedconf/date/Chen0110.1109/DATE.2001.915062https://doi.org/10.1109/DATE.2001.915062https://dblp.org/rec/conf/date/Chen01URL#6360993Sasikumar CherubalAbhijit ChatterjeeTest generation based diagnosis of device parameters for analog circuits.DATE596-6022001Conference and Workshop Papersclosedconf/date/CherubalC0110.1109/DATE.2001.915084https://doi.org/10.1109/DATE.2001.915084https://dblp.org/rec/conf/date/CherubalC01URL#6360994Chak-Chung CheungYu-Liang WuDavid Ihsin ChengFurther improve circuit partitioning using GBAW logic perturbation techniques.DATE233-2392001Conference and Workshop Papersclosedconf/date/CheungWC0110.1109/DATE.2001.915031https://doi.org/10.1109/DATE.2001.915031https://dblp.org/rec/conf/date/CheungWC01URL#6360995Ph. CheynetBogdan NicolescuRaoul VelazcoMaurizio RebaudengoMatteo Sonza ReordaMassimo ViolanteSystem safety through automatic high-level code transformations: an experimental evaluation.DATE297-3012001Conference and Workshop Papersclosedconf/date/CheynetNVRRV0110.1109/DATE.2001.915040https://doi.org/10.1109/DATE.2001.915040https://dblp.org/rec/conf/date/CheynetNVRRV01URL#6360996Silvia ChiusanoStefano Di CarloPaolo PrinettoHans-Joachim WunderlichOn applying the set covering model to reseeding.DATE156-1612001Conference and Workshop Papersclosedconf/date/ChiusanoCPW0110.1109/DATE.2001.915017https://doi.org/10.1109/DATE.2001.915017https://dblp.org/rec/conf/date/ChiusanoCPW01URL#6360997Gordon CichonWinthir BrunnbauerAnnotated data types for addressed token passing networks.DATE8012001Conference and Workshop Papersclosedconf/date/CichonB0110.1109/DATE.2001.915127https://doi.org/10.1109/DATE.2001.915127https://dblp.org/rec/conf/date/CichonB01URL#6360998George A. ConstantinidesPeter Y. K. CheungWayne LukHeuristic datapath allocation for multiple wordlength systems.DATE791-7972001Conference and Workshop Papersclosedconf/date/ConstantinidesCL0110.1109/DATE.2001.915122https://doi.org/10.1109/DATE.2001.915122https://dblp.org/rec/conf/date/ConstantinidesCL01URL#6360999Fulvio CornoMatteo Sonza ReordaGiovanni SquilleroMassimo ViolanteOn the test of microprocessor IP cores.DATE209-2132001Conference and Workshop Papersclosedconf/date/CornoRSV0110.1109/DATE.2001.915026https://doi.org/10.1109/DATE.2001.915026https://dblp.org/rec/conf/date/CornoRSV01URL#6361000Pallab DasguptaP. P. Chakrabarti 0001Amit NandiSekar KrishnaArindam ChakrabartiAbstraction of word-level linear arithmetic functions from bit-level component descriptions.DATE4-82001Conference and Workshop Papersclosedconf/date/DasguptaCNKC0110.1109/DATE.2001.914992https://doi.org/10.1109/DATE.2001.914992https://dblp.org/rec/conf/date/DasguptaCNKC01URL#6361001Thilo DemmelerPaolo GiustoA universal communication model for an automotive system integration platform.DATE47-542001Conference and Workshop Papersclosedconf/date/DemmelerG0110.1109/DATE.2001.915000https://doi.org/10.1109/DATE.2001.915000https://dblp.org/rec/conf/date/DemmelerG01URL#6361002Mohamed DessoukyAndreas KaiserMarie-Minerve LouëratAlain GreinerAnalog design for reuse - case study: very low-voltage sigma-delta modulator.DATE353-3602001Conference and Workshop Papersclosedconf/date/DessoukyKLG0110.1109/DATE.2001.915049https://doi.org/10.1109/DATE.2001.915049https://dblp.org/rec/conf/date/DessoukyKLG01URL#6361003John DielissenJef L. van MeerbergenMarco BekooijFrançoise HarmszeSergej SawitzkiJos HuiskenAlbert van der WerfPower-efficient layered turbo decoder processor.DATE246-2512001Conference and Workshop Papersclosedconf/date/DielissenMBHSHW0110.1109/DATE.2001.915033https://doi.org/10.1109/DATE.2001.915033https://dblp.org/rec/conf/date/DielissenMBHSHW01URL#6361004Alex DoboliIntegrated hardware-software co-synthesis for design of embedded systems under power and latency constraints.DATE612-6192001Conference and Workshop Papersclosedconf/date/Doboli0110.1109/DATE.2001.915087https://doi.org/10.1109/DATE.2001.915087https://dblp.org/rec/conf/date/Doboli01URL#6361005Alex DoboliRanga VemuriA regularity-based hierarchical symbolic analysis method for large-scale analog networks.DATE8062001Conference and Workshop Papersclosedconf/date/DoboliV0110.1109/DATE.2001.915132https://doi.org/10.1109/DATE.2001.915132https://dblp.org/rec/conf/date/DoboliV01URL#6361006Rainer DorschHans-Joachim WunderlichUsing mission logic for embedded testing.DATE8052001Conference and Workshop Papersclosedconf/date/DorschW0110.1109/DATE.2001.915131https://doi.org/10.1109/DATE.2001.915131https://dblp.org/rec/conf/date/DorschW01URL#6361007Alexander V. DrozdM. V. LobachevEfficient on-line testing method for a floating-point adder.DATE307-3132001Conference and Workshop Papersclosedconf/date/DrozdL0110.1109/DATE.2001.915042https://doi.org/10.1109/DATE.2001.915042https://dblp.org/rec/conf/date/DrozdL01URL#6361008George EconomakosPetros OikonomakosIoannis PanagopoulosIoannis PoulakisGeorge K. PapakonstantinouBehavioral synthesis with systemC.DATE21-252001Conference and Workshop Papersclosedconf/date/EconomakosOPPP0110.1109/DATE.2001.914995https://doi.org/10.1109/DATE.2001.914995https://dblp.org/rec/conf/date/EconomakosOPPP01URL#6361009José Alberto EspejoLuis EntrenaEnrique San MillánEmilio OlíasGeneralized reasoning scheme for redundancy addition and removal logic optimization.DATE391-3972001Conference and Workshop Papersclosedconf/date/EspejoEMO0110.1109/DATE.2001.915054https://doi.org/10.1109/DATE.2001.915054https://dblp.org/rec/conf/date/EspejoEMO01URL#6361010Michele FavalliCecilia MetraOptimization of error detecting codes for the detection of crosstalk originated errors.DATE290-2962001Conference and Workshop Papersclosedconf/date/FavalliM0110.1109/DATE.2001.915039https://doi.org/10.1109/DATE.2001.915039https://dblp.org/rec/conf/date/FavalliM01URL#6361011Sándor P. FeketeEkkehard KöhlerJürgen TeichOptimal FPGA module placement with temporal precedence constraints.DATE658-6672001Conference and Workshop Papersclosedconf/date/FeketeKT0110.1109/DATE.2001.915093https://doi.org/10.1109/DATE.2001.915093https://dblp.org/rec/conf/date/FeketeKT01URL#6361012Fabrizio FerrandiG. FerraraDonatella SciutoAlessandro FinFranco FummiFunctional test generation for behaviorally sequential models.DATE403-4102001Conference and Workshop Papersclosedconf/date/FerrandiFSFF0110.1109/DATE.2001.915056https://doi.org/10.1109/DATE.2001.915056https://dblp.org/rec/conf/date/FerrandiFSFF01URL#6361013Franco FioriSusceptibility of analog cells to substrate interference.DATE8142001Conference and Workshop Papersclosedconf/date/Fiori0110.1109/DATE.2001.915153https://doi.org/10.1109/DATE.2001.915153https://dblp.org/rec/conf/date/Fiori01URL#6361014Franco FioriFrancesco MusolinoAnalysis of EME produced by a microcontroller operation.DATE341-3472001Conference and Workshop Papersclosedconf/date/FioriM0110.1109/DATE.2001.915047https://doi.org/10.1109/DATE.2001.915047https://dblp.org/rec/conf/date/FioriM01URL#6361015Daniel GajskiEugenio VillarWolfgang RosenstielVassilios GerousisD. BartonJonas PlantinS. E. EricssonPatrizia CavalloroGjalt G. de JongC/C++: progress or deadlock in system-level specification.DATE136-1372001Conference and Workshop Papersclosedconf/date/GajskiVRGBPECJ01https://dl.acm.org/citation.cfm?id=367120https://dblp.org/rec/conf/date/GajskiVRGBPECJ01URL#6361016Youxin GaoD. F. Wong 0001A graph based algorithm for optimal buffer insertion under accurate delay models.DATE535-5392001Conference and Workshop Papersclosedconf/date/GaoW0110.1109/DATE.2001.915075https://doi.org/10.1109/DATE.2001.915075https://dblp.org/rec/conf/date/GaoW01URL#6361017Oscar GarnicaJuan LancharesRomán HermidaA pseudo delay-insensitive timing model to synthesizing low-power asynchronous circuits.DATE8102001Conference and Workshop Papersclosedconf/date/GarnicaLH0110.1109/DATE.2001.915146https://doi.org/10.1109/DATE.2001.915146https://dblp.org/rec/conf/date/GarnicaLH01URL#6361018Lovic GauthierSungjoo YooAhmed Amine JerrayaAutomatic generation and targeting of application specific operating systems and embedded systems software.DATE679-6852001Conference and Workshop Papersclosedconf/date/GauthierYJ0110.1109/DATE.2001.915098https://doi.org/10.1109/DATE.2001.915098https://dblp.org/rec/conf/date/GauthierYJ01URL#6361019Friedel GerfersYiannos ManoliA design strategy for low-voltage low-power continuous-time sigma-delta A/D converters.DATE361-3692001Conference and Workshop Papersclosedconf/date/GerfersM0110.1109/DATE.2001.915050https://doi.org/10.1109/DATE.2001.915050https://dblp.org/rec/conf/date/GerfersM01URL#6361020Ashish GianiShuo ShengMichael S. HsiaoVishwani D. AgrawalEfficient spectral techniques for sequential ATPG.DATE204-2082001Conference and Workshop Papersclosedconf/date/GianiSHA0110.1109/DATE.2001.915025https://doi.org/10.1109/DATE.2001.915025https://dblp.org/rec/conf/date/GianiSHA01URL#6361021Georges G. E. GielenDesign challenges and emerging EDA solutions in mixed-signal IC design.DATE694-6952001Conference and Workshop Papersclosedconf/date/GielenSCMR01https://dl.acm.org/citation.cfm?id=367850https://dblp.org/rec/conf/date/GielenSCMR01URL#6361022Paolo GiustoGrant MartinEdwin A. HarcourtReliable estimation of execution time of embedded software.DATE580-5892001Conference and Workshop Papersclosedconf/date/GiustoMH0110.1109/DATE.2001.915082https://doi.org/10.1109/DATE.2001.915082https://dblp.org/rec/conf/date/GiustoMH01URL#6361023Evguenii I. GoldbergMukul R. PrasadRobert K. BraytonUsing SAT for combinational equivalence checking.DATE114-1212001Conference and Workshop Papersclosedconf/date/GoldbergPB0110.1109/DATE.2001.915010https://doi.org/10.1109/DATE.2001.915010https://dblp.org/rec/conf/date/GoldbergPB01URL#6361024Peter GrunNikil D. DuttAlexandru NicolauAccess pattern based local memory customization for low power embedded systems.DATE778-7842001Conference and Workshop Papersclosedconf/date/GrunDN0110.1109/DATE.2001.915120https://doi.org/10.1109/DATE.2001.915120https://dblp.org/rec/conf/date/GrunDN01URL#6361025Amjad HajjarTom Chen 0001Isabelle MunnAnneliese Amschler AndrewsMaria BjorkmanHigh quality behavioral verification using statistical stopping criteria.DATE411-4192001Conference and Workshop Papersclosedconf/date/HajjarCMAB0110.1109/DATE.2001.915057https://doi.org/10.1109/DATE.2001.915057https://dblp.org/rec/conf/date/HajjarCMAB01URL#6361026Reiner W. HartensteinA decade of reconfigurable computing: a visionary retrospective.DATE642-6492001Conference and Workshop Papersclosedconf/date/Hartenstein0110.1109/DATE.2001.915091https://doi.org/10.1109/DATE.2001.915091https://dblp.org/rec/conf/date/Hartenstein01URL#6361027Masaki HashizumeMasahiro IchimiyaHiroyuki YotsuyanagiTakeomi TamesadaCMOS open defect detection by supply current test.DATE5092001Conference and Workshop Papersclosedconf/date/HashizumeIYT0110.1109/DATE.2001.915071https://doi.org/10.1109/DATE.2001.915071https://dblp.org/rec/conf/date/HashizumeIYT01URL#6361028Klaus HeringJork LöserJens MarkwardtdibSIM: a parallel functional logic simulator allowing dynamic load balancing.DATE472-4782001Conference and Workshop Papersclosedconf/date/HeringLM0110.1109/DATE.2001.915066https://doi.org/10.1109/DATE.2001.915066https://dblp.org/rec/conf/date/HeringLM01URL#6361029G. HettichThomas ThurnerVehicle electric/electronic architecture - one of the most important challenges for OEM's.DATE112-1132001Conference and Workshop Papersclosedconf/date/HettichT0110.1109/DATE.2001.915009https://doi.org/10.1109/DATE.2001.915009https://dblp.org/rec/conf/date/HettichT01URL#6361030Andreas Hoffmann 0002Tim KogelHeinrich MeyrA framework for fast hardware-software co-simulation.DATE760-7652001Conference and Workshop Papersclosedconf/date/HoffmanKM0110.1109/DATE.2001.915114https://doi.org/10.1109/DATE.2001.915114https://dblp.org/rec/conf/date/HoffmanKM01URL#6361031Andreas Hoffmann 0002Achim NohlStefan PeesGunnar BraunHeinrich MeyrGenerating production quality software development tools using a machine description language.DATE674-6782001Conference and Workshop Papersclosedconf/date/HoffmannNPBM0110.1109/DATE.2001.915097https://doi.org/10.1109/DATE.2001.915097https://dblp.org/rec/conf/date/HoffmannNPBM01URL#6361032Cheng-Ta HsiehLung-sheng ChenMassoud PedramMicroprocessor power analysis by labeled simulation.DATE182-1892001Conference and Workshop Papersclosedconf/date/HsiehCP0110.1109/DATE.2001.915022https://doi.org/10.1109/DATE.2001.915022https://dblp.org/rec/conf/date/HsiehCP01URL#6361033Zhining HuangSharad MalikManaging dynamic reconfiguration overhead in systems-on-a-chip design using reconfigurable datapaths and optimized interconnection networks.DATE7352001Conference and Workshop Papersclosedconf/date/HuangM0110.1109/DATE.2001.915110https://doi.org/10.1109/DATE.2001.915110https://dblp.org/rec/conf/date/HuangM01URL#6361034Alexander IrionGundolf KieferHarald P. E. VrankenHans-Joachim WunderlichCircuit partitioning for efficient logic BIST synthesis.DATE86-912001Conference and Workshop Papersclosedconf/date/IrionKVW0110.1109/DATE.2001.915005https://doi.org/10.1109/DATE.2001.915005https://dblp.org/rec/conf/date/IrionKVW01URL#6361035Anoop IyerDiana MarculescuPower aware microarchitecture resource scaling.DATE190-1962001Conference and Workshop Papersclosedconf/date/IyerM0110.1109/DATE.2001.915023https://doi.org/10.1109/DATE.2001.915023https://dblp.org/rec/conf/date/IyerM01URL#6361036Ahmed Amine JerrayaGérard MatheronElectronic system design methodology: Europe's positioning.DATE720-7212001Conference and Workshop Papersclosedconf/date/JerrayaM01https://dl.acm.org/citation.cfm?id=367903https://dblp.org/rec/conf/date/JerrayaM01URL#6361037Xu JingnanJoão C. VitalNuno HortaA Skill-based library for retargetable embedded analog cores.DATE768-7692001Conference and Workshop Papersclosedconf/date/JingnanVH0110.1109/DATE.2001.915116https://doi.org/10.1109/DATE.2001.915116https://dblp.org/rec/conf/date/JingnanVH01URL#6361038Lech JózwiakArtur ChojnackiHigh-quality sub-function construction in functional decomposition based on information relationship measures.DATE383-3902001Conference and Workshop Papersclosedconf/date/JozwiakC0110.1109/DATE.2001.915053https://doi.org/10.1109/DATE.2001.915053https://dblp.org/rec/conf/date/JozwiakC01URL#6361039Jinyong JungSungjoo YooKiyoung ChoiPerformance improvement of multi-processor systems cosimulation based on SW analysis.DATE749-7532001Conference and Workshop Papersclosedconf/date/JungYC0110.1109/DATE.2001.915112https://doi.org/10.1109/DATE.2001.915112https://dblp.org/rec/conf/date/JungYC01URL#6361040Sandeep KoranneOm Prakash GangwalOn automatic analysis of geometrically proximate nets in VSLI layout.DATE8182001Conference and Workshop Papersclosedconf/date/KoranneG0110.1109/DATE.2001.915166https://doi.org/10.1109/DATE.2001.915166https://dblp.org/rec/conf/date/KoranneG01URL#6361041P. KralicekWerner JohnHeyno GarbeModeling electromagnetic emission of integrated circuits for system analysis.DATE336-3402001Conference and Workshop Papersclosedconf/date/KralicekJG0110.1109/DATE.2001.915046https://doi.org/10.1109/DATE.2001.915046https://dblp.org/rec/conf/date/KralicekJG01URL#6361042Chidamber KulkarniC. GhezMiguel MirandaFrancky CatthoorHugo De ManCache conscious data layout organization for embedded multimedia applications.DATE686-6932001Conference and Workshop Papersclosedconf/date/KulkarniGMCM0110.1109/DATE.2001.915099https://doi.org/10.1109/DATE.2001.915099https://dblp.org/rec/conf/date/KulkarniGMCM01URL#6361043Joachim KüterErich BarkeArchitecture driven partitioning.DATE479-4872001Conference and Workshop Papersclosedconf/date/KuterB0110.1109/DATE.2001.915067https://doi.org/10.1109/DATE.2001.915067https://dblp.org/rec/conf/date/KuterB01URL#6361044Minghorng LaiD. F. Wong 0001Slicing tree is a complete floorplan representation.DATE228-2322001Conference and Workshop Papersclosedconf/date/LaiW0110.1109/DATE.2001.915030https://doi.org/10.1109/DATE.2001.915030https://dblp.org/rec/conf/date/LaiW01URL#6361045Erik LarssonZebo PengAn integrated system-on-chip test framework.DATE138-1442001Conference and Workshop Papersclosedconf/date/LarssonP0110.1109/DATE.2001.915014https://doi.org/10.1109/DATE.2001.915014https://dblp.org/rec/conf/date/LarssonP01URL#6361046Andreas LechnerAndrew Richardson 0001B. HermesTowards a better understanding of failure modes and test requirements of ADCs.DATE8032001Conference and Workshop Papersclosedconf/date/LechnerRH0110.1109/DATE.2001.915129https://doi.org/10.1109/DATE.2001.915129https://dblp.org/rec/conf/date/LechnerRH01URL#6361047Jin-Fu Li 0001Cheng-Wen WuMemory fault diagnosis by syndrome compression.DATE97-1012001Conference and Workshop Papersclosedconf/date/LiW0110.1109/DATE.2001.915007https://doi.org/10.1109/DATE.2001.915007https://dblp.org/rec/conf/date/LiW01URL#6361048Jens LienigGoeran JerkeThorsten AdlerAnalogRouter: a new approach of current-driven routing for analog circuits.DATE8192001Conference and Workshop Papersclosedconf/date/LienigJA0110.1109/DATE.2001.915167https://doi.org/10.1109/DATE.2001.915167https://dblp.org/rec/conf/date/LienigJA01URL#6361049Xun LiuMarios C. PapaefthymiouA static power estimation methodolodgy for IP-based design.DATE280-2892001Conference and Workshop Papersclosedconf/date/LiuP0110.1109/DATE.2001.915038https://doi.org/10.1109/DATE.2001.915038https://dblp.org/rec/conf/date/LiuP01URL#6361050Yi-Yu LiuKuo-Hua WangTingTing HwangC. L. Liu 0001Binary decision diagram with minimum expected path length.DATE708-7122001Conference and Workshop Papersclosedconf/date/LiuWHL0110.1109/DATE.2001.915105https://doi.org/10.1109/DATE.2001.915105https://dblp.org/rec/conf/date/LiuWHL01URL#6361051A. LockRaul CamposanoHeinrich MeyrThe programmable platform: does one size fit all?DATE226-2272001Conference and Workshop Papersclosedconf/date/LockCM01https://dl.acm.org/citation.cfm?id=367192https://dblp.org/rec/conf/date/LockCM01URL#6361052Luca MacchiaruloLuca BeniniEnrico MaciiOn-the-fly layout generation for PTL macrocells.DATE546-5512001Conference and Workshop Papersclosedconf/date/MacchiaruloBM0110.1109/DATE.2001.915077https://doi.org/10.1109/DATE.2001.915077https://dblp.org/rec/conf/date/MacchiaruloBM01URL#6361053Natividad Martínez MadridEduardo J. PeralíasAntonio J. Acosta 0001Adoración RuedaAnalog/mixed-signal IP modeling for design reuse.DATE766-7672001Conference and Workshop Papersclosedconf/date/MadridPAR0110.1109/DATE.2001.915115https://doi.org/10.1109/DATE.2001.915115https://dblp.org/rec/conf/date/MadridPAR01URL#6361054Anand MandapatiImplementation of the ATI flipper chip.DATE697-6982001Conference and Workshop Papersclosedconf/date/Mandapati0110.1109/DATE.2001.915102https://doi.org/10.1109/DATE.2001.915102https://dblp.org/rec/conf/date/Mandapati01URL#6361055Radu MarculescuAmit NandiProbabilistic application modeling for system-level perfromance analysis.DATE572-5792001Conference and Workshop Papersclosedconf/date/MarculescuN0110.1109/DATE.2001.915081https://doi.org/10.1109/DATE.2001.915081https://dblp.org/rec/conf/date/MarculescuN01URL#6361056Ting Zhang 0001Luca BeniniGiovanni De MicheliComponent selection and matching for IP-based design.DATE40-462001Conference and Workshop Papersclosedconf/date/MartinSZBM0110.1109/DATE.2001.914999https://doi.org/10.1109/DATE.2001.914999https://dblp.org/rec/conf/date/MartinSZBM01URL#6361057Shin-ichi MinatoShinya IshiharaStreaming BDD manipulation for large-scale combinatorial problems.DATE702-7072001Conference and Workshop Papersclosedconf/date/MinatoI0110.1109/DATE.2001.915104https://doi.org/10.1109/DATE.2001.915104https://dblp.org/rec/conf/date/MinatoI01URL#6361058José Manuel MoyaFrancisco MoyaJuan Carlos López 0001A hardware-software operating system for heterogeneous designs.DATE8202001Conference and Workshop Papersclosedconf/date/MoyaML0110.1109/DATE.2001.915169https://doi.org/10.1109/DATE.2001.915169https://dblp.org/rec/conf/date/MoyaML01URL#6361059Srinath R. NaiduE. T. A. F. JacobsMinimizing stand-by leakage power in static CMOS circuits.DATE370-3762001Conference and Workshop Papersclosedconf/date/NaiduJ0110.1109/DATE.2001.915051https://doi.org/10.1109/DATE.2001.915051https://dblp.org/rec/conf/date/NaiduJ01URL#6361060Gi-Joon NamKarem A. SakallahRob A. RutenbarA boolean satisfiability-based incremental rerouting approach with application to FPGAs.DATE560-5652001Conference and Workshop Papersclosedconf/date/NamSR0110.1109/DATE.2001.915079https://doi.org/10.1109/DATE.2001.915079https://dblp.org/rec/conf/date/NamSR01URL#6361061Susumu NaritaSH-4 RISC microprocessor for multimedia, game machine.DATE699-7012001Conference and Workshop Papersclosedconf/date/Narita0110.1109/DATE.2001.915103https://doi.org/10.1109/DATE.2001.915103https://dblp.org/rec/conf/date/Narita01URL#6361062Anshuman NayakMalay HaldarAlok N. ChoudharyPrithviraj BanerjeePrecision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs.DATE722-7282001Conference and Workshop Papersclosedconf/date/NayakHCB0110.1109/DATE.2001.915108https://doi.org/10.1109/DATE.2001.915108https://dblp.org/rec/conf/date/NayakHCB01URL#6361063Cassondra NeauKhurram MuhammadKaushik Roy 0001Low complexity FIR filters using factorization of perturbed coefficients.DATE268-2722001Conference and Workshop Papersclosedconf/date/NeauMR0110.1109/DATE.2001.915036https://doi.org/10.1109/DATE.2001.915036https://dblp.org/rec/conf/date/NeauMR01URL#6361064Luong NguyenVincent JanicotSimulation method to extract characteristics for digital wireless communication systems.DATE176-1812001Conference and Workshop Papersclosedconf/date/NguyenJ0110.1109/DATE.2001.915021https://doi.org/10.1109/DATE.2001.915021https://dblp.org/rec/conf/date/NguyenJ01URL#6361065Gabriela NicolescuSungjoo YooAhmed Amine JerrayaMixed-level cosimulation for fine gradual refinement of communication in SoC design.DATE754-7592001Conference and Workshop Papersclosedconf/date/NicolescuYJ0110.1109/DATE.2001.915113https://doi.org/10.1109/DATE.2001.915113https://dblp.org/rec/conf/date/NicolescuYJ01URL#6361066Nicola NicoliciBashir M. Al-HashimiTestability trade-offs for BIST RTL data paths: the case for three dimensional design space.DATE8022001Conference and Workshop Papersclosedconf/date/NicoliciA0110.1109/DATE.2001.915128https://doi.org/10.1109/DATE.2001.915128https://dblp.org/rec/conf/date/NicoliciA01URL#6361067Juanjo NogueraRosa M. BadiaA HW/SW partitioning algorithm for dynamically reconfigurable architectures.DATE7292001Conference and Workshop Papersclosedconf/date/NogueraB0110.1109/DATE.2001.915109https://doi.org/10.1109/DATE.2001.915109https://dblp.org/rec/conf/date/NogueraB01URL#6361068Yakov NovikovEvguenii I. GoldbergAn efficient learning procedure for multiple implication checks.DATE127-1352001Conference and Workshop Papersclosedconf/date/NovikovG0110.1109/DATE.2001.915012https://doi.org/10.1109/DATE.2001.915012https://dblp.org/rec/conf/date/NovikovG01URL#6361069Markus OlbrichAchim ReinErich BarkeAn improved hierarchical classification algorithm for structural analysis of integrated circuits.DATE8072001Conference and Workshop Papersclosedconf/date/OlbrichRB0110.1109/DATE.2001.915134https://doi.org/10.1109/DATE.2001.915134https://dblp.org/rec/conf/date/OlbrichRB01URL#6361070Iyad OuaissRanga VemuriHierarchical memory mapping during synthesis in FPGA-based reconfigurable computers.DATE650-6572001Conference and Workshop Papersclosedconf/date/OuaissV0110.1109/DATE.2001.915092https://doi.org/10.1109/DATE.2001.915092https://dblp.org/rec/conf/date/OuaissV01URL#6361071Arjun PandayDamien CoudercSimon MarichalarAIL: description of a global electronic architecture at the vehicle scale.DATE1122001Conference and Workshop Papersclosedconf/date/PandayCM01https://dl.acm.org/citation.cfm?id=367107https://dblp.org/rec/conf/date/PandayCM01URL#6361072Sri ParameswaranCode placement in hardware/software co-synthesis to improve performance and reduce cost.DATE626-6322001Conference and Workshop Papersclosedconf/date/Parameswaran0110.1109/DATE.2001.915089https://doi.org/10.1109/DATE.2001.915089https://dblp.org/rec/conf/date/Parameswaran01URL#6361073Antonis M. PaschalisDimitris GizopoulosNektarios KranitisMihalis PsarakisYervant ZorianDeterministic software-based self-testing of embedded processor cores.DATE92-962001Conference and Workshop Papersclosedconf/date/PaschalisGKPZ0110.1109/DATE.2001.915006https://doi.org/10.1109/DATE.2001.915006https://dblp.org/rec/conf/date/PaschalisGKPZ01URL#6361074Claudio PasseroneYosinori WatanabeLuciano LavagnoGeneration of minimal size code for scheduling graphs.DATE668-6732001Conference and Workshop Papersclosedconf/date/PasseroneWL0110.1109/DATE.2001.915096https://doi.org/10.1109/DATE.2001.915096https://dblp.org/rec/conf/date/PasseroneWL01URL#6361075Pierre G. PaulinFaraydon KarimPaul BromleyNetwork processors: a perspective on market requirements, processor architectures and embedded S/W tools.DATE420-4292001Conference and Workshop Papersclosedconf/date/PaulinKB0110.1109/DATE.2001.915058https://doi.org/10.1109/DATE.2001.915058https://dblp.org/rec/conf/date/PaulinKB01URL#6361076Christian PiguetMarc RenaudinThierry J.-F. OmnésLow-power systems on chips (SOCs).DATE4882001Conference and Workshop Papersclosedconf/date/PiguetRO0110.1109/DATE.2001.915068https://doi.org/10.1109/DATE.2001.915068https://dblp.org/rec/conf/date/PiguetRO01URL#6361077Carlos A. Alba PintoBart MesmanKoen van EijkJochen A. G. JessConstraint satisfaction for storage files with Fifos or stacks during scheduling.DATE8242001Conference and Workshop Papersclosedconf/date/PintoMEJ0110.1109/DATE.2001.915176https://doi.org/10.1109/DATE.2001.915176https://dblp.org/rec/conf/date/PintoMEJ01URL#6361078Irith PomeranzSudhakar M. ReddySequence reordering to improve the levels of compaction achievable by static compaction procedures.DATE214-2182001Conference and Workshop Papersclosedconf/date/PomeranzR0110.1109/DATE.2001.915027https://doi.org/10.1109/DATE.2001.915027https://dblp.org/rec/conf/date/PomeranzR01URL#6361079Irith PomeranzSudhakar M. ReddyDefinitions of the numbers of detections of target faults and their effectiveness in guiding test generation for high defect coverage.DATE504-5082001Conference and Workshop Papersclosedconf/date/PomeranzR01a10.1109/DATE.2001.915070https://doi.org/10.1109/DATE.2001.915070https://dblp.org/rec/conf/date/PomeranzR01aURL#6361080Md. Saffat QuasemSandeep K. Gupta 0001Exact fault simulation for systems on Silicon that protects each core's intellectual property.DATE8042001Conference and Workshop Papersclosedconf/date/QuasemG0110.1109/DATE.2001.915130https://doi.org/10.1109/DATE.2001.915130https://dblp.org/rec/conf/date/QuasemG01URL#6361081Sherief RedaA. SalemCombinational equivalence checking using Boolean satisfiability and binary decision diagrams.DATE122-1262001Conference and Workshop Papersclosedconf/date/RedaS0110.1109/DATE.2001.915011https://doi.org/10.1109/DATE.2001.915011https://dblp.org/rec/conf/date/RedaS01URL#6361082Rocío del RíoJosep Lluís de la RosaFernando MedeiroMaria Belen Pérez-VerdúÁngel Rodríguez-VázquezTop-down design of a xDSL 14-bit 4MS/s sigma-delta modulator in digital CMOS technology.DATE348-3522001Conference and Workshop Papersclosedconf/date/RioRMPR0110.1109/DATE.2001.915048https://doi.org/10.1109/DATE.2001.915048https://dblp.org/rec/conf/date/RioRMPR01URL#6361083Marco RonaGunter KramplModelling SoC devices for virtual test using VHDL.DATE770-7712001Conference and Workshop Papersclosedconf/date/RonaK0110.1109/DATE.2001.915117https://doi.org/10.1109/DATE.2001.915117https://dblp.org/rec/conf/date/RonaK01URL#6361084C. RousselleMatthias PflanzA. BehlingT. MohauptHeinrich Theodor VierhausA register-transfer-level fault simulator for permanent and transient faults in embedded processors.DATE8112001Conference and Workshop Papersclosedconf/date/RoussellePBMV0110.1109/DATE.2001.915148https://doi.org/10.1109/DATE.2001.915148https://dblp.org/rec/conf/date/RoussellePBMV01URL#6361085Jürgen RufDirk W. HoffmannJoachim GerlachThomas KropfWolfgang RosenstielWolfgang Müller 0003The simulation semantics of systemC.DATE64-702001Conference and Workshop Papersclosedconf/date/RufHGKRM0110.1109/DATE.2001.915002https://doi.org/10.1109/DATE.2001.915002https://dblp.org/rec/conf/date/RufHGKRM01URL#6361086Jürgen RufDirk W. HoffmannThomas KropfWolfgang RosenstielSimulation-guided property checking based on a multi-valued AR-automata.DATE742-7482001Conference and Workshop Papersclosedconf/date/RufHKR0110.1109/DATE.2001.915111https://doi.org/10.1109/DATE.2001.915111https://dblp.org/rec/conf/date/RufHKR01URL#6361087Paulino Ruiz-de-ClavijoJorge Juan-ChicoManuel J. BellidoAntonio J. Acosta 0001Manuel Valencia-BarreroHALOTIS: high accuracy LOgic TIming simulator with inertial and degradation delay model.DATE467-4712001Conference and Workshop Papersclosedconf/date/Ruiz-de-ClavijoJBAV0110.1109/DATE.2001.915065https://doi.org/10.1109/DATE.2001.915065https://dblp.org/rec/conf/date/Ruiz-de-ClavijoJBAV01URL#6361088Makoto SaitohMasaaki AzumaAtsushi Takahashi 0001Clustering based fast clock scheduling for light clock-tree.DATE240-2452001Conference and Workshop Papersclosedconf/date/SaitohAT0110.1109/DATE.2001.915032https://doi.org/10.1109/DATE.2001.915032https://dblp.org/rec/conf/date/SaitohAT01URL#6361089Mariagiovanna SamiDonatella SciutoCristina SilvanoVittorio ZaccariaRoberto ZafalonExploiting data forwarding to reduce the power budget of VLIW embedded processors.DATE252-2572001Conference and Workshop Papersclosedconf/date/SamiSSZZ0110.1109/DATE.2001.915034https://doi.org/10.1109/DATE.2001.915034https://dblp.org/rec/conf/date/SamiSSZZ01URL#6361090Probir SarkarCheng-Kok KohRepeater block planning under simultaneous delay and transition time constraints.DATE540-5452001Conference and Workshop Papersclosedconf/date/SarkarK0110.1109/DATE.2001.915076https://doi.org/10.1109/DATE.2001.915076https://dblp.org/rec/conf/date/SarkarK01URL#6361091Eike SchmidtGerd JochensLars KruseFrans TheeuwenWolfgang NebelAutomatic nonlinear memory power modelling.DATE8082001Conference and Workshop Papersclosedconf/date/SchmidtJKTN0110.1109/DATE.2001.915135https://doi.org/10.1109/DATE.2001.915135https://dblp.org/rec/conf/date/SchmidtJKTN01URL#6361092Tatjana SerdarCarl SechenAutomatic datapath tile placement and routing.DATE552-5592001Conference and Workshop Papersclosedconf/date/SerdarS0110.1109/DATE.2001.915078https://doi.org/10.1109/DATE.2001.915078https://dblp.org/rec/conf/date/SerdarS01URL#6361093Dongkun ShinJihong Kim 0001Naehyuck ChangAn operation rearrangement technique for power optimization in VLIM instruction fetch.DATE8092001Conference and Workshop Papersclosedconf/date/ShinKC0110.1109/DATE.2001.915137https://doi.org/10.1109/DATE.2001.915137https://dblp.org/rec/conf/date/ShinKC01URL#6361094Robert SiegmundDietmar Müller 0001SystemCSV - an extension of SystemC for mixed multi-level communication modeling and interface-based system design.DATE26-332001Conference and Workshop Papersclosedconf/date/SiegmundM0110.1109/DATE.2001.914996https://doi.org/10.1109/DATE.2001.914996https://dblp.org/rec/conf/date/SiegmundM01URL#6361095Julio Leao da Silva Jr.J. ShambergerM. Josie AmmerChunlong GuoSuet-Fei LiRahul C. ShahTim TuanMichael SheetsJan M. RabaeyBorivoje NikolicAlberto L. Sangiovanni-VincentelliPaul K. WrightDesign methodology for PicoRadio networks.DATE314-3252001Conference and Workshop Papersclosedconf/date/SilvaSAGLSTSRNSW0110.1109/DATE.2001.915043https://doi.org/10.1109/DATE.2001.915043https://dblp.org/rec/conf/date/SilvaSAGLSTSRNSW01URL#6361096Peter van StaaThomas BeckEmbedded tutorial: current trends in the design of automotive electronic systems.DATE38-392001Conference and Workshop Papersclosedconf/date/StaaB0110.1109/DATE.2001.914998https://doi.org/10.1109/DATE.2001.914998https://dblp.org/rec/conf/date/StaaB01URL#6361097Hans-Ulrich HeidbrinkData management: limiter or accelerator for electronic design creativity.DATE162-1632001Conference and Workshop Papersclosedconf/date/StaaBHPMKH01https://dl.acm.org/citation.cfm?id=367132https://dblp.org/rec/conf/date/StaaBHPMKH01URL#6361098Arie van StaverenChris J. M. VerhoevenOrder determination for frequency compensation of negative-feedback systems.DATE8152001Conference and Workshop Papersclosedconf/date/StaverenV0110.1109/DATE.2001.915155https://doi.org/10.1109/DATE.2001.915155https://dblp.org/rec/conf/date/StaverenV01URL#6361099Vytautas StuikysGiedrius ZiberkasRobertas DamaseviciusGiedrius MajauskasTwo approaches for developing generic components in VHDL.DATE8002001Conference and Workshop Papersclosedconf/date/StuikysZDM0110.1109/DATE.2001.915126https://doi.org/10.1109/DATE.2001.915126https://dblp.org/rec/conf/date/StuikysZDM01URL#6361100Kjetil SvarstadGabriela NicolescuAhmed Amine JerrayaA model for describing communication between aggregate objects in the specification and design of embedded systems.DATE77-852001Conference and Workshop Papersclosedconf/date/SvarstadNJ0110.1109/DATE.2001.915004https://doi.org/10.1109/DATE.2001.915004https://dblp.org/rec/conf/date/SvarstadNJ01URL#6361101Haruyuki TagoKazuhiro HashimotoNobuyuki IkumiMasato NagamatsuMasakazu SuzuokiYasuyuki YamamotoCPU for PlayStation 2.DATE6962001Conference and Workshop Papersclosedconf/date/TagoHINSY0110.1109/DATE.2001.915101https://doi.org/10.1109/DATE.2001.915101https://dblp.org/rec/conf/date/TagoHINSY01URL#6361102Elena TeicaRajesh RadhakrishnanRanga VemuriOn the verification of synthesized designs using automatically generated transformational witnesses.DATE7982001Conference and Workshop Papersclosedconf/date/TeicaRV0110.1109/DATE.2001.915123https://doi.org/10.1109/DATE.2001.915123https://dblp.org/rec/conf/date/TeicaRV01URL#6361103Andrei Sergeevich TerechkoEvert-Jan D. PolJos T. J. van EijndhovenPRMDL: a machine description language for clustered VLIW architectures.DATE8212001Conference and Workshop Papersclosedconf/date/TerechkoPE0110.1109/DATE.2001.915170https://doi.org/10.1109/DATE.2001.915170https://dblp.org/rec/conf/date/TerechkoPE01URL#6361104Mitchell A. ThorntonRolf DrechslerSpectral decision diagrams using graph transformations.DATE713-7192001Conference and Workshop Papersclosedconf/date/ThorntonD0110.1109/DATE.2001.915106https://doi.org/10.1109/DATE.2001.915106https://dblp.org/rec/conf/date/ThorntonD01URL#6361105Raimund UbarArtur JutmanZebo PengTiming simulation of digital circuits with binary decision diagrams.DATE460-4662001Conference and Workshop Papersclosedconf/date/UbarJP0110.1109/DATE.2001.915063https://doi.org/10.1109/DATE.2001.915063https://dblp.org/rec/conf/date/UbarJP01URL#6361106Piet VanasscheGeorges G. E. GielenWilly M. C. SansenEfficient time-domain simulation of telecom frontends using a complex damped exponential signal model.DATE169-1752001Conference and Workshop Papersclosedconf/date/VanasscheGS0110.1109/DATE.2001.915020https://doi.org/10.1109/DATE.2001.915020https://dblp.org/rec/conf/date/VanasscheGS01URL#6361107Gerd VandersteenPiet WambacqYves RolainJohan SchoukensStéphane DonnayMarc EngelsIvo BolsensEfficient bit-error-rate estimation of multicarrier transceivers.DATE164-1682001Conference and Workshop Papersclosedconf/date/VandersteenWRSDEB0110.1109/DATE.2001.915019https://doi.org/10.1109/DATE.2001.915019https://dblp.org/rec/conf/date/VandersteenWRSDEB01URL#6361108Mauricio VareaBashir M. Al-HashimiDual transitions petri net based modelling technique for embedded systems specification.DATE566-5712001Conference and Workshop Papersclosedconf/date/VareaA0110.1109/DATE.2001.915080https://doi.org/10.1109/DATE.2001.915080https://dblp.org/rec/conf/date/VareaA01URL#6361109Michael G. WahlAnthony P. AmblerChristoph MaaßMohammed RahmanFrom DFT to systems test - a model based cost optimization tool.DATE302-3062001Conference and Workshop Papersclosedconf/date/WahlAMR0110.1109/DATE.2001.915041https://doi.org/10.1109/DATE.2001.915041https://dblp.org/rec/conf/date/WahlAMR01URL#6361110Piet WambacqGerd VandersteenJoel R. PhillipsJaijeet S. RoychowdhuryWolfgang EberleBaolin YangDavid E. LongAlper Demir 0001CAD for RF circuits.DATE520-5292001Conference and Workshop Papersclosedconf/date/WambacqVPREYLD0110.1109/DATE.2001.915073https://doi.org/10.1109/DATE.2001.915073https://dblp.org/rec/conf/date/WambacqVPREYLD01URL#6361111Chr. WernerRalf GoettscheA. WörnerUlrich RamacherCrosstalk noise in future digital CMOS circuits.DATE331-3352001Conference and Workshop Papersclosedconf/date/WernerGWR0110.1109/DATE.2001.915045https://doi.org/10.1109/DATE.2001.915045https://dblp.org/rec/conf/date/WernerGWR01URL#6361112Ron WilsonManaging the SoC design challenge with "Soft" hardware.DATE610-6112001Conference and Workshop Papersclosedconf/date/Wilson0110.1109/DATE.2001.915086https://doi.org/10.1109/DATE.2001.915086https://dblp.org/rec/conf/date/Wilson01URL#6361113Chun WongPaul MarchalPeng YangFrancky CatthoorHugo De ManAggeliki S. PrayatiNathalie CossementRudy LauwereinsDiederik VerkestTask concurrency management methodology summary.DATE8132001Conference and Workshop Papersclosedconf/date/WongMYCMPCLV0110.1109/DATE.2001.915151https://doi.org/10.1109/DATE.2001.915151https://dblp.org/rec/conf/date/WongMYCMPCLV01URL#6361114Alexander WormHolger LammNorbert WehnDesign of low-power high-speed maximum a priori decoder architectures.DATE258-2672001Conference and Workshop Papersclosedconf/date/WormLW0110.1109/DATE.2001.915035https://doi.org/10.1109/DATE.2001.915035https://dblp.org/rec/conf/date/WormLW01URL#6361115Yuan Xie 0001Wayne H. WolfAllocation and scheduling of conditional task graph in hardware/software co-synthesis.DATE620-6252001Conference and Workshop Papersclosedconf/date/XieW0110.1109/DATE.2001.915088https://doi.org/10.1109/DATE.2001.915088https://dblp.org/rec/conf/date/XieW01URL#6361116Qinwei XuPinaki MazumderEfficient and passive modeling of transmission lines by using differential quadrature method.DATE437-4442001Conference and Workshop Papersclosedconf/date/XuM0110.1109/DATE.2001.915060https://doi.org/10.1109/DATE.2001.915060https://dblp.org/rec/conf/date/XuM01URL#6361117C. YeungAnssi HaverinenGraham MatthewsJonathan MorrisJauher ZaidiStandard bus vs. bus wrapper: what is the best solution for future SoC integration?DATE776-7772001Conference and Workshop Papersclosedconf/date/YeungHMMZ01https://dl.acm.org/citation.cfm?id=367970https://dblp.org/rec/conf/date/YeungHMMZ01URL#6361118Erhan YildizArie van StaverenChris J. M. VerhoevenMinimizing the number of floating bias voltage sources with integer linear programming.DATE8162001Conference and Workshop Papersclosedconf/date/YildizSV0110.1109/DATE.2001.915163https://doi.org/10.1109/DATE.2001.915163https://dblp.org/rec/conf/date/YildizSV01URL#6361119Qingjian YuErnest S. KuhExplicit formulas and efficient algorithm for moment computation of coupled RC trees with lumped and distributed elements.DATE445-4502001Conference and Workshop Papersclosedconf/date/YuK0110.1109/DATE.2001.915061https://doi.org/10.1109/DATE.2001.915061https://dblp.org/rec/conf/date/YuK01URL#6361120Jing ZengMagdy S. AbadirJayanta BhadraJacob A. AbrahamFull chip false timing path identification: applications to the PowerPCTM microprocessors.DATE514-5192001Conference and Workshop Papersclosedconf/date/ZengABA0110.1109/DATE.2001.915072https://doi.org/10.1109/DATE.2001.915072https://dblp.org/rec/conf/date/ZengABA01URL#6361121Zhihong ZengPriyank KallaMaciej J. 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TeixeiraCarlos Eduardo PereiraOctávio Páscoa DiasJorge SemiãoPeter MuhmenthalerW. RadermacherEmbedded tutorial: TRP: integrating embedded test and ATE.DATE34-372001Conference and Workshop Papersclosedconf/date/ZorianPTTPDSMR01https://dl.acm.org/citation.cfm?id=367081https://dblp.org/rec/conf/date/ZorianPTTPDSMR01URL#6361126Wolfgang NebelAhmed JerrayaProceedings of the Conference on Design, Automation and Test in Europe, DATE 2001, Munich, Germany, March 12-16, 2001DATEIEEE Computer Society2001Editorshipconf/date/2001https://ieeexplore.ieee.org/xpl/conhome/7307/proceedinghttps://dblp.org/rec/conf/date/2001URL#6399802