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"Design of Low Power Multiplier with Less Area Using Quaternary Carry ..."

K. Gavaskar et al. (2023)

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DOI: 10.1007/S11277-022-10006-7

access: closed

type: Journal Article

metadata version: 2023-01-31

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  - https://dblp.org/rec/journals/wpc/GavaskarMRPRS23
K. Gavaskar, D. Malathi, G. Ravivarma, P. S. Priyatharshan, S. Rajeshwari, B. Sanjay:
Design of Low Power Multiplier with Less Area Using Quaternary Carry Increment Adder for New-Fangled Processors. Wirel. Pers. Commun. 128(2): 1417-1435 (2023)

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