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"A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in ..."

Xingjun Wu et al. (2003)

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DOI: 10.1023/A:1021110405895

access: closed

type: Journal Article

metadata version: 2020-05-20

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  - journals/vlsisp/WuCSG03
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  - https://dblp.org/rec/journals/vlsisp/WuCSG03
Xingjun Wu, Hongyi Chen, Yihe Sun, Weixin Gai:
A Fully-Pipeline Linear Systolic Architecture for Modular Multiplier in Public-Key Crypto-Systems. J. VLSI Signal Process. 33(1-2): 191-197 (2003)

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