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"An efficient tree architecture for modulo 2n+1 ..."

Zhongde Wang, Graham A. Jullien, William C. Miller (1996)

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DOI: 10.1007/BF00929618

access: closed

type: Journal Article

metadata version: 2020-05-20

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  - journals/vlsisp/WangJM96
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  - https://dblp.org/rec/journals/vlsisp/WangJM96
Zhongde Wang, Graham A. Jullien, William C. Miller:
An efficient tree architecture for modulo 2ⁿ+1 multiplication. J. VLSI Signal Process. 14(3): 241-248 (1996)

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