"High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC ..."

Roberto R. Osorio, Javier D. Bruguera (2013)

> Home

Details and statistics

DOI: 10.1007/S11265-012-0718-Y

access: closed

type: Journal Article

metadata version: 2020-03-12

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/vlsisp/OsorioB13
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsisp/OsorioB13
Roberto R. Osorio, Javier D. Bruguera:
High-Speed FPGA Architecture for CABAC Decoding Acceleration in H.264/AVC Standard. J. Signal Process. Syst. 72(2): 119-132 (2013)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.