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"A shift register architecture for high-speed data sorting."

Chen-Yi Lee, Jer-Min Tsai (1995)

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DOI: 10.1007/BF02107058

access: closed

type: Journal Article

metadata version: 2020-05-20

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  - journals/vlsisp/LeeT95
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  - https://dblp.org/rec/journals/vlsisp/LeeT95
Chen-Yi Lee, Jer-Min Tsai:
A shift register architecture for high-speed data sorting. J. VLSI Signal Process. 11(3): 273-280 (1995)

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