"New Bit-Parallel Systolic Architectures for Computing Multiplication, ..."

Chiou-Yng Lee, Che Wun Chiou (2008)

> Home

Details and statistics

DOI: 10.1007/S11265-008-0164-Z

access: closed

type: Journal Article

metadata version: 2020-03-12

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/vlsisp/LeeC08
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsisp/LeeC08
Chiou-Yng Lee, Che Wun Chiou:
New Bit-Parallel Systolic Architectures for Computing Multiplication, Multiplicative Inversion and Division in GF(2^m) Under Polynomial Basis and Normal Basis Representations. J. Signal Process. Syst. 52(3): 313-324 (2008)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.