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"Design and Implementation of Viterbi Decoder with FPGAs."

M. Kivioja, Jouni Isoaho, L. Vänskä (1999)

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DOI: 10.1023/A:1008067404215

access: closed

type: Journal Article

metadata version: 2020-05-20

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  dblp key:
  - journals/vlsisp/KiviojaIV99
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  - https://dblp.org/rec/journals/vlsisp/KiviojaIV99
M. Kivioja, Jouni Isoaho, L. Vänskä:
Design and Implementation of Viterbi Decoder with FPGAs. J. VLSI Signal Process. 21(1): 5-14 (1999)

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