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"An efficient bit-level systolic cell design for finite ring digital signal ..."

Graham A. Jullien et al. (1989)

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DOI: 10.1007/BF02427794

access: closed

type: Journal Article

metadata version: 2020-05-20

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  - https://dblp.org/rec/journals/vlsisp/JullienBCTM89
Graham A. Jullien, P. D. Bird, J. T. Carr, Majid Taheri, William C. Miller:
An efficient bit-level systolic cell design for finite ring digital signal processing applications. J. VLSI Signal Process. 1(3): 189-207 (1989)

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