"A unified partitioning and scheduling scheme for mapping multi-stage ..."

Yin-Tsung Hwang, Yu Hen Hu (1995)

> Home

Details and statistics

DOI: 10.1007/BF02106827

access: closed

type: Journal Article

metadata version: 2020-05-20

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/vlsisp/HwangH95
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsisp/HwangH95
Yin-Tsung Hwang, Yu Hen Hu:
A unified partitioning and scheduling scheme for mapping multi-stage regular iterative algorithms onto processor arrays. J. VLSI Signal Process. 11(1-2): 133-150 (1995)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.