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"Low-Power Parallel Video Compression Architecture for a Single-Chip ..."

Jeff Y. F. Hsieh, Teresa H.-Y. Meng (1999)

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DOI: 10.1023/A:1008006400249

access: closed

type: Journal Article

metadata version: 2020-05-20

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  - journals/vlsisp/HsiehM99
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  - https://dblp.org/rec/journals/vlsisp/HsiehM99
Jeff Y. F. Hsieh, Teresa H.-Y. Meng:
Low-Power Parallel Video Compression Architecture for a Single-Chip Digital CMOS Camera. J. VLSI Signal Process. 21(3): 195-207 (1999)

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