"Statistical Module Level Area and Delay Estimation."

Akhilesh Tyagi (1997)

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DOI: 10.1155/1997/78238

access: open

type: Journal Article

metadata version: 2022-11-05

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Akhilesh Tyagi:
Statistical Module Level Area and Delay Estimation. VLSI Design 5(2): 141-153 (1997)

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