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"Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability."

Steffen Tarnick (1998)

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DOI: 10.1155/1998/67574

access: open

type: Journal Article

metadata version: 2022-11-04

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  - https://dblp.org/rec/journals/vlsi/Tarnick98
Steffen Tarnick:
Embedded Parity and Two-Rail TSC Checkers with Error-Memorizing Capability. VLSI Design 5(4): 347-356 (1998)

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