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"Design and Implementation of a Low Power Ternary Full Adder."

A. Srivastava, K. Venkatapathy (1996)

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DOI: 10.1155/1996/94696

access: open

type: Journal Article

metadata version: 2022-11-07

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  dblp key:
  - journals/vlsi/SrivastavaV96
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  - https://dblp.org/rec/journals/vlsi/SrivastavaV96
A. Srivastava, K. Venkatapathy:
Design and Implementation of a Low Power Ternary Full Adder. VLSI Design 4(1): 75-81 (1996)

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