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"Area and Power Modeling for Networks-on-Chip with Layout Awareness."

Paolo Meloni et al. (2007)

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DOI: 10.1155/2007/50285

access: open

type: Journal Article

metadata version: 2020-03-27

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  - journals/vlsi/MeloniLACBRB07
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  - https://dblp.org/rec/journals/vlsi/MeloniLACBRB07
Paolo Meloni, Igor Loi, Federico Angiolini, Salvatore Carta, Massimo Barbaro, Luigi Raffo, Luca Benini:
Area and Power Modeling for Networks-on-Chip with Layout Awareness. VLSI Design 2007: 50285:1-50285:12 (2007)

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