Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using ..."

S. Jayanthy, M. C. Bhuvaneswari, Keesarapalli Sujitha (2012)

> Home

Details and statistics

DOI: 10.1155/2012/745861

access: open

type: Journal Article

metadata version: 2019-06-02

- view
  - electronic edition via DOI (open access)
  authority control:
- export record
  dblp key:
  - journals/vlsi/JayanthyBS12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/vlsi/JayanthyBS12
S. Jayanthy, M. C. Bhuvaneswari, Keesarapalli Sujitha:
Test Generation for Crosstalk-Induced Delay Faults in VLSI Circuits Using Modified FAN Algorithm. VLSI Design 2012: 745861:1-745861:10 (2012)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.