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"An Efficient Hardware Accelerator for Structured Sparse Convolutional ..."

Chaoyang Zhu et al. (2020)

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DOI: 10.1109/TVLSI.2020.3002779

access: closed

type: Journal Article

metadata version: 2020-09-19

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  - https://dblp.org/rec/journals/tvlsi/ZhuHYZZS20
Chaoyang Zhu, Kejie Huang, Shuyuan Yang, Ziqi Zhu, Hejia Zhang, Haibin Shen:
An Efficient Hardware Accelerator for Structured Sparse Convolutional Neural Networks on FPGAs. IEEE Trans. Very Large Scale Integr. Syst. 28(9): 1953-1965 (2020)

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