"A 65-nm CMOS Downconverter-Less Clock Generator Architecture Using Voltage ..."

You Wu et al. (2025)

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DOI: 10.1109/TVLSI.2025.3583337

access: open

type: Journal Article

metadata version: 2025-11-02

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You Wu, Kei Awano, Kento Okamura, Teruaki Ono, Kohei Sakamoto, Hiroaki Kitaike, Hironori Tagawa, Jin Nakamura, Masaya Kaneko, Yuta Kimura, Hiroaki Nakamura, Shufan Xu, Ruilin Zhang, Kunyang Liu, Hirofumi Shinohara, Kiichi Niitsu:
A 65-nm CMOS Downconverter-Less Clock Generator Architecture Using Voltage Stacking of Oscillator and Frequency Dividers for Scaling-Friendly IoTs. IEEE Trans. Very Large Scale Integr. Syst. 33(10): 2668-2679 (2025)

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