"STT-RAM Cache Hierarchy With Multiretention MTJ Designs."

Zhenyu Sun et al. (2014)

> Home

Details and statistics

DOI: 10.1109/TVLSI.2013.2267754

access: closed

type: Journal Article

metadata version: 2023-06-26

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tvlsi/SunBLWZ14
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/SunBLWZ14
Zhenyu Sun, Xiuyuan Bi, Hai Li, Weng-Fai Wong, Xiaochun Zhu:
STT-RAM Cache Hierarchy With Multiretention MTJ Designs. IEEE Trans. Very Large Scale Integr. Syst. 22(6): 1281-1293 (2014)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.