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"A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power ..."

Qing Liu, Wei Shu, Joseph S. Chang (2017)

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DOI: 10.1109/TVLSI.2017.2747132

access: closed

type: Journal Article

metadata version: 2020-03-11

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  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/LiuSC17
Qing Liu, Wei Shu, Joseph S. Chang:
A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS. IEEE Trans. Very Large Scale Integr. Syst. 25(12): 3444-3454 (2017)

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