"Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, ..."

Ming-Yi Lin, Wei-Kuan Chiang, Chin-Hung Wang (2025)

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DOI: 10.1109/TVLSI.2025.3581296

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type: Journal Article

metadata version: 2025-09-11

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Ming-Yi Lin, Wei-Kuan Chiang, Chin-Hung Wang:
Enhancing Memory BIST With an Optimized RTL-BIST IP Core: A Low-Power, High-Fault-Coverage Approach. IEEE Trans. Very Large Scale Integr. Syst. 33(9): 2556-2569 (2025)

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