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"Design of an Area-Effcient Million-Bit Integer Multiplier Using Double ..."

Xiang Feng, Shuguo Li (2017)

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DOI: 10.1109/TVLSI.2017.2691727

access: closed

type: Journal Article

metadata version: 2020-03-11

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  persistent URL:
  - https://dblp.org/rec/journals/tvlsi/FengL17
Xiang Feng, Shuguo Li:
Design of an Area-Effcient Million-Bit Integer Multiplier Using Double Modulus NTT. IEEE Trans. Very Large Scale Integr. Syst. 25(9): 2658-2662 (2017)

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