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"Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance."

Yiran Chen et al. (2010)

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DOI: 10.1109/TVLSI.2009.2026280

access: closed

type: Journal Article

metadata version: 2022-07-04

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  - https://dblp.org/rec/journals/tvlsi/ChenLKSLXR10
Yiran Chen, Hai Li, Cheng-Kok Koh, Guangyu Sun, Jing Li, Yuan Xie, Kaushik Roy:
Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1621-1624 (2010)

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