![](https://dblp1.uni-trier.de/img/logo.ua.320x120.png)
![](https://dblp1.uni-trier.de/img/dropdown.dark.16x16.png)
![](https://dblp1.uni-trier.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp1.uni-trier.de/img/search.dark.16x16.png)
![search dblp](https://dblp1.uni-trier.de/img/search.dark.16x16.png)
default search action
"A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration ..."
Fujun Bai et al. (2023)
- Fujun Bai
, Song Wang, Xuerong Jia, Yixin Guo, Bing Yu, Hang Wang
, Cong Lai, Qiwei Ren, Hongbin Sun
:
A Low-Cost Reduced-Latency DRAM Architecture With Dynamic Reconfiguration of Row Decoder. IEEE Trans. Very Large Scale Integr. Syst. 31(1): 128-141 (2023)
![](https://dblp1.uni-trier.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.