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"A process-tolerant cache architecture for improved yield in nanoscale ..."

Amit Agarwal et al. (2005)

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DOI: 10.1109/TVLSI.2004.840407

access: closed

type: Journal Article

metadata version: 2020-10-26

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Amit Agarwal, Bipul Chandra Paul, Hamid Mahmoodi-Meimand, Animesh Datta, Kaushik Roy:
A process-tolerant cache architecture for improved yield in nanoscale technologies. IEEE Trans. Very Large Scale Integr. Syst. 13(1): 27-38 (2005)

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