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"Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA."

Yun Wu, John McAllister (2018)

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DOI: 10.1109/TPDS.2017.2746081

access: closed

type: Journal Article

metadata version: 2020-10-02

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  dblp key:
  - journals/tpds/WuM18
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  persistent URL:
  - https://dblp.org/rec/journals/tpds/WuM18
Yun Wu, John McAllister:
Architectural Synthesis of Multi-SIMD Dataflow Accelerators for FPGA. IEEE Trans. Parallel Distributed Syst. 29(1): 43-55 (2018)

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