![](https://dblp1.uni-trier.de/img/logo.ua.320x120.png)
![](https://dblp1.uni-trier.de/img/dropdown.dark.16x16.png)
![](https://dblp1.uni-trier.de/img/peace.dark.16x16.png)
Остановите войну!
for scientists:
![search dblp search dblp](https://dblp1.uni-trier.de/img/search.dark.16x16.png)
![search dblp](https://dblp1.uni-trier.de/img/search.dark.16x16.png)
default search action
"Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on ..."
Zhe Jiang et al. (2024)
- Zhe Jiang
, Kecheng Yang
, Nathan Fisher
, Nan Guan
, Neil C. Audsley
, Zheng Dong
:
Hopscotch: A Hardware-Software Co-Design for Efficient Cache Resizing on Multi-Core SoCs. IEEE Trans. Parallel Distributed Syst. 35(1): 89-104 (2024)
![](https://dblp1.uni-trier.de/img/cog.dark.24x24.png)
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.