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"Run-time performance optimization of an FPGA-based deduction engine for ..."

Andreas Dandalis, Viktor K. Prasanna (2002)

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DOI: 10.1145/605440.605444

access: closed

type: Journal Article

metadata version: 2018-11-06

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Andreas Dandalis, Viktor K. Prasanna:
Run-time performance optimization of an FPGA-based deduction engine for SAT solvers. ACM Trans. Design Autom. Electr. Syst. 7(4): 547-562 (2002)

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