Stop the war!

Остановите войну!

for scientists:

default search action

combined dblp search
author search
venue search
publication search

ask others

"Power and latency efficient mechanism: a seamless bridge between buffered ..."

Jing Lin, Xiaola Lin (2012)

> Home

Details and statistics

DOI: 10.1007/S11227-011-0676-3

access: closed

type: Journal Article

metadata version: 2020-05-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tjs/LinL12
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tjs/LinL12
Jing Lin, Xiaola Lin:
Power and latency efficient mechanism: a seamless bridge between buffered and bufferless routing in on-chip network. J. Supercomput. 61(3): 1048-1067 (2012)

a service of

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.