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"A parallel elliptic curve crypto-processor architecture with reduced clock ..."
Murugesan Kalaiarasi et al. (2022)
- Murugesan Kalaiarasi, Vepadappu Raman Venkatasubramani, V. Vinoth Thyagarajan, S. Rajaram:
A parallel elliptic curve crypto-processor architecture with reduced clock cycle for FPGA platforms. J. Supercomput. 78(13): 15567-15597 (2022)
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