"FPGA realization of a neural-network-based nonlinear channel equalizer."

Chin-Tsu Yen, Wan-De Weng, Yen Tsun Lin (2004)

> Home

Details and statistics

DOI: 10.1109/TIE.2004.825221

access: closed

type: Journal Article

metadata version: 2020-05-22

- view
  - electronic edition via DOI
  - unpaywalled version
  authority control:
- export record
  dblp key:
  - journals/tie/YenWL04
- ask others
- share record
  persistent URL:
  - https://dblp.org/rec/journals/tie/YenWL04
Chin-Tsu Yen, Wan-De Weng, Yen Tsun Lin:
FPGA realization of a neural-network-based nonlinear channel equalizer. IEEE Trans. Ind. Electron. 51(2): 472-479 (2004)

manage site settings

To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.