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"Ultralow-Latency Hardware-in-the-Loop Platform for Rapid Validation of ..."

Dusan Majstorovic et al. (2011)

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DOI: 10.1109/TIE.2011.2112318

access: closed

type: Journal Article

metadata version: 2023-09-30

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Dusan Majstorovic, Ivan Celanovic, Nikola Dj. Teslic, Nikola L. Celanovic, Vladimir A. Katic:
Ultralow-Latency Hardware-in-the-Loop Platform for Rapid Validation of Power Electronics Designs. IEEE Trans. Ind. Electron. 58(10): 4708-4716 (2011)

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