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"Exploiting Timing Error Resilience in Processor Architecture."

John Sartori, Rakesh Kumar (2013)

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DOI: 10.1145/2465787.2465791

access: closed

type: Journal Article

metadata version: 2020-09-08

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John Sartori, Rakesh Kumar:
Exploiting Timing Error Resilience in Processor Architecture. ACM Trans. Embed. Comput. Syst. 12(2s): 89:1-89:25 (2013)

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